Design and simulation of addressable failure site test structure for IC process control monitor

Abstract

A novel test structure to ensure failure addressable and high-density test structure of semiconductor process control monitor with a limited number of contact pads required for electrical test is described. The placement and routing scheme requires only two levels of conductive layers, and provides the maximum number of bridging and continuity test structure units. A graph model is developed to manifest the spatial configuration of test structure units and simplify the complexity of fault detection. Also, a generic algorithm of multi-fault detection was developed.