{"title":"数字信号处理器的发展趋势","authors":"S.A. Mujtaba","doi":"10.1109/VTSA.1999.786012","DOIUrl":null,"url":null,"abstract":"To facility the implementation of complex signal processing algorithms future DSPs will be required to deliver higher performance and ease of programmability without compromising power dissipation and code density. To meet these conflicting requirements, several architectures have been proposed such as EPIC, VLIW, and superscalar. In this paper, we chart the evolution of DSPs-starting from a simple Multiply-Accumulate engine and progressing to a system-on-a-chip embodying some variant of a parallel processing machine.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"419 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Trends in digital signal processors\",\"authors\":\"S.A. Mujtaba\",\"doi\":\"10.1109/VTSA.1999.786012\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To facility the implementation of complex signal processing algorithms future DSPs will be required to deliver higher performance and ease of programmability without compromising power dissipation and code density. To meet these conflicting requirements, several architectures have been proposed such as EPIC, VLIW, and superscalar. In this paper, we chart the evolution of DSPs-starting from a simple Multiply-Accumulate engine and progressing to a system-on-a-chip embodying some variant of a parallel processing machine.\",\"PeriodicalId\":237214,\"journal\":{\"name\":\"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)\",\"volume\":\"419 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTSA.1999.786012\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.1999.786012","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
To facility the implementation of complex signal processing algorithms future DSPs will be required to deliver higher performance and ease of programmability without compromising power dissipation and code density. To meet these conflicting requirements, several architectures have been proposed such as EPIC, VLIW, and superscalar. In this paper, we chart the evolution of DSPs-starting from a simple Multiply-Accumulate engine and progressing to a system-on-a-chip embodying some variant of a parallel processing machine.