H. Koike, H. Takato, K. Hiyama, S. Yoshida, H. Harakawa, K. Kokubun, T. Shimabukuro, S. Kato, M. Tamaoki, H. Okano, H. Sato, Y. Morimasa, T. Yamamoto, M. Tanaka, J. Kumagai, O. Yakabe, H. Naruse, H. Kamijo, K. Tomioka, H. Ishiuchi
{"title":"完全集成的嵌入式DRAM技术，具有高性能逻辑和用于片上系统的商品DRAM单元","authors":"H. Koike, H. Takato, K. Hiyama, S. Yoshida, H. Harakawa, K. Kokubun, T. Shimabukuro, S. Kato, M. Tamaoki, H. Okano, H. Sato, Y. Morimasa, T. Yamamoto, M. Tanaka, J. Kumagai, O. Yakabe, H. Naruse, H. Kamijo, K. Tomioka, H. Ishiuchi","doi":"10.1109/VTSA.1999.786045","DOIUrl":null,"url":null,"abstract":"This paper demonstrates a process integration for high performance and small footprint embedded DRAMs. A trench capacitor cell and a self-aligned bit line contact are selected to maintain exactly the same size as commodity DRAM cells. The cell array region is covered with a thin SiN barrier against salicidation. Ti-salicide source/drain is used in the logic region. No retention time degradation and good circuit performance are confirmed.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Fully integrated embedded DRAM technologies with high performance logic and commodity DRAM cells for system-on-a-chip\",\"authors\":\"H. Koike, H. Takato, K. Hiyama, S. Yoshida, H. Harakawa, K. Kokubun, T. Shimabukuro, S. Kato, M. Tamaoki, H. Okano, H. Sato, Y. Morimasa, T. Yamamoto, M. Tanaka, J. Kumagai, O. Yakabe, H. Naruse, H. Kamijo, K. Tomioka, H. Ishiuchi\",\"doi\":\"10.1109/VTSA.1999.786045\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper demonstrates a process integration for high performance and small footprint embedded DRAMs. A trench capacitor cell and a self-aligned bit line contact are selected to maintain exactly the same size as commodity DRAM cells. The cell array region is covered with a thin SiN barrier against salicidation. Ti-salicide source/drain is used in the logic region. No retention time degradation and good circuit performance are confirmed.\",\"PeriodicalId\":237214,\"journal\":{\"name\":\"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTSA.1999.786045\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.1999.786045","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fully integrated embedded DRAM technologies with high performance logic and commodity DRAM cells for system-on-a-chip
This paper demonstrates a process integration for high performance and small footprint embedded DRAMs. A trench capacitor cell and a self-aligned bit line contact are selected to maintain exactly the same size as commodity DRAM cells. The cell array region is covered with a thin SiN barrier against salicidation. Ti-salicide source/drain is used in the logic region. No retention time degradation and good circuit performance are confirmed.
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