用于生成快速并行乘法器的高效合成器

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI:10.1109/VTSA.1999.786001

Shen-Fu Hsiao, M.-R. Jiang

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引用次数: 2

摘要

开发了一种自动生成器，可合成任意位精度的定点乘法器，其速度性能可与近期其他全定制设计相媲美。该合成器对压缩单元的互连进行全局优化，以最小化部分积和树的延迟。

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An efficient synthesizer for generation of fast parallel multipliers

An automatic generator is developed which can synthesize fixed-point multipliers of any bit accuracy with speed performance comparable to other recent full-custom designs. This synthesizer performs global optimization on the interconnection of compression elements to minimize the delay in the partial product summation tree.

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来源期刊

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

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