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2010 IEEE International SOI Conference (SOI)最新文献

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Ultra thin fully depleted active pixel sensors processed on SOI wafers 在SOI晶圆上加工的超薄全耗尽有源像素传感器
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641059
L. Andricek, G. Liemann, H. Moser, R. Richter, B. Schweinfest
{"title":"Ultra thin fully depleted active pixel sensors processed on SOI wafers","authors":"L. Andricek, G. Liemann, H. Moser, R. Richter, B. Schweinfest","doi":"10.1109/SOI.2010.5641059","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641059","url":null,"abstract":"The production of the latest generation of fully depleted DEPFET active pixel sensors designed for the Belle-II experiment at KEK, Japan, is currently being finalized. For the first time a thinning technology based on SOI wafers finds now its application in a high energy physics experiment. The DEPFET (DEpleted P-channel FET) is a field effect transistor with an additional implant underneath the channel and integrated on a fully depleted substrate. It combines the functions of a detector and the first amplification stage in one single device. The in-sensor amplification makes it possible to create very thin sensors with an excellent signal/noise ratio for minimum ionizing particles. The fabrication of thin wafer-scale active pixel sensors requires the combination of a highly specialized MOS technology, including two poly-silicon and three metal layers, on fully depleted bulk with MEMS technologies. The devices are realized on custom-made SOI wafers with structured back side implant supplied by Soitec, France. Initially developed for thin DEPFETs, the technology is now being used for the production of other high performance sensors in High Energy Physics (strip and passive pixel detectors) and photon counting devices based on Geiger-mode avalanche photo diodes. Other fields of application are all kind of thin imaging devices for low energy particles (electron microscopy or in medical hadron therapy).","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123427734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
HiSIM-SOI: Complete surface-potential-based model valid for all SOI-structure types HiSIM-SOI:完全基于表面电位的模型，适用于所有soi结构类型
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641416
M. Miura-Mattausch, S. Amakawa, M. Miyake, H. Kikuchihara, S. Baba, H. Mattausch
{"title":"HiSIM-SOI: Complete surface-potential-based model valid for all SOI-structure types","authors":"M. Miura-Mattausch, S. Amakawa, M. Miyake, H. Kikuchihara, S. Baba, H. Mattausch","doi":"10.1109/SOI.2010.5641416","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641416","url":null,"abstract":"The compact SOI-MOSFET model HiSIM-SOI based on the complete surface-potential description is presented. The model considers all possible charges induced in the device for the formulation of the Poisson equation, which is solved iteratively. Thus HiSIM-SOI is valid for any structural variations from thick to extremely thin SOI or BOX layers. The dynamic depletion between the fully and partially depleted conditions is well reproduced. It is also demonstrated that the floating-body effect can be accurately captured by considering the accumulated charge in the SOI layer for the solution of the Poisson equation. HiSIM-SOI is verified to correctly reproduce 2D-device simulation results automatically for different SOI-structure types without any additional option setting.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116898300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Integrated radiation image sensors with SOI technology 采用SOI技术的集成辐射图像传感器
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641403
Y. Arai, T. Miyoshi, R. Ichimiya, K. Hara, Y. Onuki
{"title":"Integrated radiation image sensors with SOI technology","authors":"Y. Arai, T. Miyoshi, R. Ichimiya, K. Hara, Y. Onuki","doi":"10.1109/SOI.2010.5641403","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641403","url":null,"abstract":"We have developed monolithic radiation detectors based on a 0.2 µm Fully-Depleted Silicon-on-Insulator (FD-SOI) CMOS technology. It has both a thick, high-resistivity sensor layer and a thin LSI circuit layer in a single chip. To shield the electronics part from the sensor region, we have created a buried well region under the buried oxide (BOX) layer of the SOI wafer. Two type of detectors, integration and counting types, are being developed.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130819654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical and thermal characterization of 150 mm Silicon-on-polycrystalline-Silicon Carbide hybrid substrates 150毫米硅-多晶-碳化硅混合衬底的电学和热特性
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641380
S. Lotfi, Ö. Vallin, Ling-Guang Li, L. Vestling, Hans Norström, Jörgen Olsson
{"title":"Electrical and thermal characterization of 150 mm Silicon-on-polycrystalline-Silicon Carbide hybrid substrates","authors":"S. Lotfi, Ö. Vallin, Ling-Guang Li, L. Vestling, Hans Norström, Jörgen Olsson","doi":"10.1109/SOI.2010.5641380","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641380","url":null,"abstract":"150 mm Silicon-on-polycrystalline-Silicon Carbide (poly-SiC) hybrid substrates, without intermediate oxide layers have been realized by hydrophilic wafer bonding of SOI- and poly-SiC wafers. A novel rapid thermal treatment step has been introduced before furnace annealing to avoid bubble formation, cracks and breakage. The final substrates are shown to be stress-free. Electrical and thermal characterization of devices manufactured on the substrate using a MOS process show excellent performance.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129926561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Comparison between the behavior of submicron graded-channel SOI nMOSFETs with fully- and partially-depleted operations in a wide temperature range 亚微米梯度沟道SOI nmosfet在宽温度范围内完全耗尽和部分耗尽的性能比较
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641388
M. Souza, M. Emam, D. Vanhoenacker-Janvier, Jean-Pierre Raskin, Denis Flandre, M. Pavanello
{"title":"Comparison between the behavior of submicron graded-channel SOI nMOSFETs with fully- and partially-depleted operations in a wide temperature range","authors":"M. Souza, M. Emam, D. Vanhoenacker-Janvier, Jean-Pierre Raskin, Denis Flandre, M. Pavanello","doi":"10.1109/SOI.2010.5641388","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641388","url":null,"abstract":"In this work electrical properties of GC SOI nMOSFETs from two different technologies were presented for temperatures ranging between 90K and 380K. It has been shown that the increase of mobility with temperature reduction is larger than for devices with lighter dopind levels. Heavily doped GC from transistors shown constant threshold voltage over the entire temperature range, as it lies close to the ZTC point. Although the temperature lowering leads devices to operate in full depletion, GC devices with thin gate oxide presented GIFBE effect due to the leakage current reduction. The subthreshold swing of heavily doped GC transistors have shown to depart the theoretical limit for T higher than 250K, indicating a change in the operation mode from fully to partially-depleted.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124492806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fin shape influence on the analog performance of standard and strained MuGFETs 翅片形状对标准和应变mugfet模拟性能的影响
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641387
R. Buhler, J. Martino, P. Agopian, R. Giacomini, E. Simoen, C. Claeys
{"title":"Fin shape influence on the analog performance of standard and strained MuGFETs","authors":"R. Buhler, J. Martino, P. Agopian, R. Giacomini, E. Simoen, C. Claeys","doi":"10.1109/SOI.2010.5641387","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641387","url":null,"abstract":"From the analog performance perspective, there is a fin cross-section shape influence on electric parameters. At weak inversion levels the gm/ID is shape dependent, while for moderate and strong inversions the strain type is dominant, where the mobility starts to play an important role. The output conductance and the Early voltage show a strong dependence on both fin shape and strain type. For thinner Wmid there is a performance increase of up to 3 dB on intrinsic voltage gain compared to rectangular shape. Strained devices present better AV and fT, both following the gm tendency for each channel length.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129206885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
ESD robustness of FDSOI gated diode for ESD network design: Thin or thick BOX? 用于ESD网络设计的FDSOI门控二极管的ESD稳健性:薄盒还是厚盒?
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641372
T. Benoist, C. Fenouillet-Béranger, P. Perreau, C. Buj, P. Galy, D. Marin-Cudraz, O. Faynot, S. Cristoloveanu, P. Gentil
{"title":"ESD robustness of FDSOI gated diode for ESD network design: Thin or thick BOX?","authors":"T. Benoist, C. Fenouillet-Béranger, P. Perreau, C. Buj, P. Galy, D. Marin-Cudraz, O. Faynot, S. Cristoloveanu, P. Gentil","doi":"10.1109/SOI.2010.5641372","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641372","url":null,"abstract":"The robustness against Electrostatic Discharge (ESD) events of gated diodes, fabricated in CMOS 45nm FDSOI technology, is compared for 10nm and 145nm Buried Oxide (BOX) thickness. It is shown that the performance of devices for co-design on thin BOX is improved thanks to a better thermal dissipation: A gain of 1.6 on the robustness was found.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"573 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117347582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Timing verification of a 45nm SOI standard cell library 45nm SOI标准细胞库的时序验证
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641402
J. Pelloie, Y. Laplanche, C. Hawkins, Roma Kundu
{"title":"Timing verification of a 45nm SOI standard cell library","authors":"J. Pelloie, Y. Laplanche, C. Hawkins, Roma Kundu","doi":"10.1109/SOI.2010.5641402","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641402","url":null,"abstract":"A reliable timing verification methodology has been developed and proven on a 45nm SOI standard cell library. This methodology is currently used at more advanced process nodes.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"105 7S 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134119888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of millimeter-wave mixed signal circuits in 45nm SOI CMOS 45nm SOI CMOS毫米波混合信号电路设计
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641062
J. Popp, B. Kormanyos, M. Adams, A. Hurtado, J. Braatz, C. Wolfhausen, T. McKay
{"title":"Design of millimeter-wave mixed signal circuits in 45nm SOI CMOS","authors":"J. Popp, B. Kormanyos, M. Adams, A. Hurtado, J. Braatz, C. Wolfhausen, T. McKay","doi":"10.1109/SOI.2010.5641062","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641062","url":null,"abstract":"This work details the benefits of ultra deep submicron (UDSM) SOI CMOS technology for high performance mixed signal circuits at mm-wave frequencies. In particular, a mm-wave Direct Digital Synthesizer (DDS) design in 45nm partially depleted (PD) SOI CMOS is presented with post extraction simulated performance of 32 Gsps sample rate that rivals state of the art III–V DDS performance. Technology benefits of the 45nm PD-SOI technology's billion transistor integration, sub-5pS digital gate delays, and measured ∼400GHz ft/∼200GHz fmax cutoff frequency performance is highlighted. Increasing design challenges for UDSM CMOS mm-wave mixed signal circuits caused by increased gate leakage, limited transistor output impedance, inadequate foundry models, and required checking for design manufacturability are also addressed.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127935345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimization of RTA process for PVD-TiN gate FinFETs PVD-TiN栅极finfet的RTA工艺优化
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641382
Y. Liu, T. Kamei, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, T. Matsukawa, K. Sakamoto, A. Ogura, M. Masahara
{"title":"Optimization of RTA process for PVD-TiN gate FinFETs","authors":"Y. Liu, T. Kamei, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, T. Matsukawa, K. Sakamoto, A. Ogura, M. Masahara","doi":"10.1109/SOI.2010.5641382","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641382","url":null,"abstract":"T<inf>R</inf> dependence of the electrical characteristics have systematically been investigated by fabricating PVD-TiN gate FinFETs. It was found that optimal T<inf>R</inf> is 915 °C for setting symmetrical V<inf>th</inf> with a higher I<inf>ON</inf> and the smallest σV<inf>th</inf>. It was also confirmed that carrier mobilities are independet of T<inf>R</inf> and comparable to those in the case of n<sup>+</sup>-poly-Si gate. The n<sup>+</sup>-poly-Si capping on PVD-TiN gate is very useful to set symmetrical V<inf>th</inf> for undoped FinFETs without mobility degradation.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126883193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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