PVD-TiN栅极finfet的RTA工艺优化

2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI:10.1109/SOI.2010.5641382

Y. Liu, T. Kamei, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, T. Matsukawa, K. Sakamoto, A. Ogura, M. Masahara

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引用次数: 0

摘要

通过制作PVD-TiN栅极finfet，系统地研究了电特性与TR的依赖关系。结果表明，当离子浓度较高、σVth最小时，对称Vth的最佳温度为915℃。还证实了载流子迁移率与TR无关，与n+-多晶硅栅极的迁移率相当。PVD-TiN栅极上的n+-多晶硅封盖对于在不降低迁移率的情况下设置未掺杂finfet的对称v值非常有用。

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Optimization of RTA process for PVD-TiN gate FinFETs

TR dependence of the electrical characteristics have systematically been investigated by fabricating PVD-TiN gate FinFETs. It was found that optimal TR is 915 °C for setting symmetrical Vth with a higher ION and the smallest σVth. It was also confirmed that carrier mobilities are independet of TR and comparable to those in the case of n⁺-poly-Si gate. The n⁺-poly-Si capping on PVD-TiN gate is very useful to set symmetrical Vth for undoped FinFETs without mobility degradation.

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2010 IEEE International SOI Conference (SOI)

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