2010 IEEE International SOI Conference (SOI)最新文献

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High-frequency characterization of intrinsic FinFET channel 本征FinFET通道的高频特性
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641064
H. Sakai, S. O'Uchi, T. Matsukawa, K. Endo, Y. Liu, T. Tsukada, Y. Ishikawa, T. Nakagawa, T. Sekigawa, H. Koike, K. Sakamoto, M. Masahara, H. Ishikuro
{"title":"High-frequency characterization of intrinsic FinFET channel","authors":"H. Sakai, S. O'Uchi, T. Matsukawa, K. Endo, Y. Liu, T. Tsukada, Y. Ishikawa, T. Nakagawa, T. Sekigawa, H. Koike, K. Sakamoto, M. Masahara, H. Ishikuro","doi":"10.1109/SOI.2010.5641064","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641064","url":null,"abstract":"The extraction method of the high-frequency characteristics of the intrinsic part of FinFET was experimentally demonstrated. By using an open, short, and through pattern optimized for FinFET process, the parasitic components of the source, drain and gate area were successfully deembedded. Using the proposed method, the fT of the FinFET with Lg=120nm, Tox=2nm, and TFin=50nm was estimated to be 85GHz which coincided with the simulated results by the device model.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115168358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Non-linear analysis of n-type Schottky-Barrier MOSFETs n型肖特基势垒mosfet的非线性分析
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641391
J. Tinoco, C. Urban, M. Emam, S. Mantl, Q. Zhao, J. Raskin
{"title":"Non-linear analysis of n-type Schottky-Barrier MOSFETs","authors":"J. Tinoco, C. Urban, M. Emam, S. Mantl, Q. Zhao, J. Raskin","doi":"10.1109/SOI.2010.5641391","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641391","url":null,"abstract":"In the last few years, many efforts have been made looking for the improvement of the DC and RF performance of MOS transistors. In this scope, Schottky-Barrier transistors appear as very interesting alternative to conventional devices. In this paper we present the non-linear behavior of dopant segregated n-type SB-MOSFETs with 180 nm channel length.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125360031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Photonic integrated circuits in silicon-on-insulator 绝缘体上硅的光子集成电路
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641404
W. Bogaerts, S. Selvaraja, P. Dumon, P. Absil, D. van Thourhout, R. Baets
{"title":"Photonic integrated circuits in silicon-on-insulator","authors":"W. Bogaerts, S. Selvaraja, P. Dumon, P. Absil, D. van Thourhout, R. Baets","doi":"10.1109/SOI.2010.5641404","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641404","url":null,"abstract":"We show a platform for silicon photonic circuits in silicon-on-insulator. In crystalline silicon waveguides have very low propagation losses and at the same time extremely good uniformity, which is essential for high-quality wavelength filters. Also, we can use deposited amorphous material to fabricate similar devices on top of any substrate (including CMOS) with only a small penalty in performance.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122561694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The use of high resolution haze for control of SOI surface roughness in a volume production environment. 在批量生产环境中使用高分辨率雾霾来控制SOI表面粗糙度。
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641056
R. Brun, C. Moulin, G. Bast, G. Simpson, P. Dighe
{"title":"The use of high resolution haze for control of SOI surface roughness in a volume production environment.","authors":"R. Brun, C. Moulin, G. Bast, G. Simpson, P. Dighe","doi":"10.1109/SOI.2010.5641056","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641056","url":null,"abstract":"It is well known that the final surface roughness of SOI wafers has to be controlled to a very tight tolerance in order to maintain transistor parameters required for today's advanced node semiconductor devices. The traditional method for this measurement is to use an atomic force microscope (AFM), but the tool's throughput and the area sampled by each measurement are very limited, and AFM repeatability is low. Such measurements can be used during process development, but are not practical during high-volume production.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129089990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ultra low power, harsh environment SOI-CMOS design of temperature sensor based threshold detection and wake-up IC 超低功耗,恶劣环境SOI-CMOS设计基于温度传感器的阈值检测和唤醒IC
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641369
M. Assaad, P. Gérard, L. Francis, D. Flandre
{"title":"Ultra low power, harsh environment SOI-CMOS design of temperature sensor based threshold detection and wake-up IC","authors":"M. Assaad, P. Gérard, L. Francis, D. Flandre","doi":"10.1109/SOI.2010.5641369","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641369","url":null,"abstract":"An ultra-low-power temperature-sensor-based silicon-on-insulator (SOI) CMOS Integrated Circuit (IC) for harsh environment application is presented. It first detects a temperature threshold, secondly generates a wake-up signal that turns on a data-acquisition microprocessor once the threshold has been detected and thirdly operates as a temperature sensor in a harsh environment while being wired to the microprocessor kept in a safe area. The IC is continuously on for a very long period of time and is required to be powered from a ultrathin battery type, hence must be an ultra low power design. It includes a diode-based temperature sensor, a quasi-temperature independent voltage generator, a comparator and a power switch to limit the microprocessor stand-by consumption. Since our application is mainly for harsh environment (e.g. high temperature, radiation), the chip has been designed using the 1-µm high-temperature SOI-CMOS XFAB technology; it occupies an area of 560µm×165µm. The biasing current and power dissipation are 4.12 µA and 20.6 µW respectively at a supply voltage of 5V and temperature of 27°C, according to the post-layout transistor level simulation results.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124652094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Compound semiconductors on silicon for future generation VLSI 用于下一代超大规模集成电路的硅基化合物半导体
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641048
R. Hill, A. Baraskar, C. Park, J. Barnett, P. Majhi, R. Jammy
{"title":"Compound semiconductors on silicon for future generation VLSI","authors":"R. Hill, A. Baraskar, C. Park, J. Barnett, P. Majhi, R. Jammy","doi":"10.1109/SOI.2010.5641048","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641048","url":null,"abstract":"The superior electron mobility and velocity offered by compound semiconductors makes them attractive materials to fill the performance gap expected between strained Si and the product requirements for high performance with low power. The heterointegration of these materials on a silicon platform using a VLSI compatible process flow is necessary for cost effectiveness and manufacturability. This paper demonstrates a planar hetero-buffer integration scheme, with mobility of 8000 cm2/Vs - approaching the mobility of homo-integrated HEMTs on InP substrates. Devices were fabricated on a 200 mm substrate using a fully VLSI compatible process flow with a state of the art Si toolset. The encouraging device performance and excellent uniformity demonstrates that III–V can be integrated in a standard Si VLSI production line.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121233049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Hybrid silicon lasers: Integration of III–V and silicon photonics using wafer bonding 混合硅激光器:利用晶圆键合集成III-V和硅光子学
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641405
R. Jones, H. Park, A. Fang, M. Sysak, B. Koch, D. Liang, H. Chang, J. Bowers
{"title":"Hybrid silicon lasers: Integration of III–V and silicon photonics using wafer bonding","authors":"R. Jones, H. Park, A. Fang, M. Sysak, B. Koch, D. Liang, H. Chang, J. Bowers","doi":"10.1109/SOI.2010.5641405","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641405","url":null,"abstract":"This talk will give an overview of the hybrid silicon laser device platform which heterogeneously integrates InP with SOI to fabricate silicon photonic chips with integrated lasers. Challenges associated with this integration will be discussed as well as examples of integrating hybrid silicon lasers with other silicon photonic components on the path to achieving a terabit silicon photonic link.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130836905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Disruptive ultra-low-power SOI CMOS circuits towards μW medical sensor implants 面向μW医用传感器植入的突破性超低功耗SOI CMOS电路
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641370
G. Gosset, D. Bol, G. Pollissard-Quatremex0300re, B. Rue, D. Flandre
{"title":"Disruptive ultra-low-power SOI CMOS circuits towards μW medical sensor implants","authors":"G. Gosset, D. Bol, G. Pollissard-Quatremex0300re, B. Rue, D. Flandre","doi":"10.1109/SOI.2010.5641370","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641370","url":null,"abstract":"In this paper, we propose disruptive circuit design techniques for ultra-low-power (ULP) medical sensor implants. They use unique CMOS blocks to build ULP diodes and transistors that are implemented with ultra-low-Vt devices in 0.15µm fully-depleted SOI CMOS, without process modification. Using these techniques, we propose a highly-efficient power-management unit and a 1.1µW interface for capacitive sensors.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132258697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Total-ionizing-dose radiation response of partially-depleted SOI devices 部分耗尽SOI器件的总电离剂量辐射响应
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641057
N. Rezzak, E. Zhang, M. Alles, peixiong zhao, H. Hughes
{"title":"Total-ionizing-dose radiation response of partially-depleted SOI devices","authors":"N. Rezzak, E. Zhang, M. Alles, peixiong zhao, H. Hughes","doi":"10.1109/SOI.2010.5641057","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641057","url":null,"abstract":"The high body doping inherent in sub-100 nm partially-depleted SOI devices tends to mitigate the sensitivity to TID-induced leakage, providing that the doping reaches the STI sidewalls and back channel. Measured TID response on 45 nm NMOS SOI is consistent with trends observed in simulations.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115492042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Total dose radiation response of a 45nm SOI Technology 45nm SOI技术的总剂量辐射响应
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641052
S. T. Liu, A. Hurst, H. Hughes, P. McMarr, J. Benedito, C. Capasso
{"title":"Total dose radiation response of a 45nm SOI Technology","authors":"S. T. Liu, A. Hurst, H. Hughes, P. McMarr, J. Benedito, C. Capasso","doi":"10.1109/SOI.2010.5641052","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641052","url":null,"abstract":"Based on the TID evaluation using Co-60 radiation source, we conclude that both gate oxide and the buried oxide of core 45nm SOI technology are robust. Investigation of radiation properties of the edge effect of the core devices and the input-output devices are necessary to have a complete assessment of the 45nm SOI technology. This will be done in the future.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123912483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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