P. Goyal, S. Gupta, R. Krishnan, W. Davies, H. Ho, A. Tessier, A. Arya, S. Deshpande, S. Fang, S. Lee, Z. Li, J. Liu, R. Takalkar, J. Dadson, A. Chakravarti, A. Domenicucci, J. Shepard, K. McStay, B. Morgenfeld, S. Allen, X. Li, B. Khan, R. Knarr, R. Arndt, R. Venigalla, P. Parries, M. Chudzik, S. Stiffler
{"title":"Characterization of novel TiN/HfO2 metal insulator semiconductor stack for 32nm eDRAM","authors":"P. Goyal, S. Gupta, R. Krishnan, W. Davies, H. Ho, A. Tessier, A. Arya, S. Deshpande, S. Fang, S. Lee, Z. Li, J. Liu, R. Takalkar, J. Dadson, A. Chakravarti, A. Domenicucci, J. Shepard, K. McStay, B. Morgenfeld, S. Allen, X. Li, B. Khan, R. Knarr, R. Arndt, R. Venigalla, P. Parries, M. Chudzik, S. Stiffler","doi":"10.1109/SOI.2010.5641378","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641378","url":null,"abstract":"In this paper, we describe the unique scaling challenges, critical sources of variation, and the potential trench leakage mechanisms of 32nm trench capacitors that utilize high-к/metal electrode materials. This is the first eDRAM technology that has successfully integrated high-к and metal films as part of the trench capacitor. In addition, these films are found to be fully compatible with front-end of line (FEOL) thermal budgets. We explore sources of variation and illustrate process mitigation techniques, including the targeting of key capacitor properties, and reduction in trench leakage. Finally, we illustrate that systematic and random variations do not pose as insurmountable barriers, and that the trench technology is scalable to the 22nm trench and beyond.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131215504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Vitale, J. Kedzierski, P. Wyatt, M. Renzi, C. Keast
{"title":"FDSOI metal gate transistors for ultra low power subthreshold operation","authors":"S. Vitale, J. Kedzierski, P. Wyatt, M. Renzi, C. Keast","doi":"10.1109/SOI.2010.5641399","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641399","url":null,"abstract":"A workfunction-tuned TiN metal gate is integrated into ultra-low-power FDSOI CMOS transistors, optimized for subthreshold operation at 0.3 V. The workfunction of the TiN metal gate is tunable across the mid-gap range, by adjusting deposition parameters and post-deposition annealing. The transistors show 71% reduction in Cgd and 55% reduction in Vt variation, compared to conventional FDSOI transistors of the same size. A 59% decrease in switching energy and a 91% decrease in stage delay is demonstrated in ring oscillators fabricated with the subthreshold-optimized FDSOI transistors when compared to commercial bulk silicon devices.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128118597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Sano, S. Kamisaka, K. Yoshinaga, H. Mimura, S. Matsuyama, K. Yamauchi
{"title":"Numerically controlled sacrificial plasma oxidation using array of electrodes for improving thickness uniformity of SOI","authors":"Y. Sano, S. Kamisaka, K. Yoshinaga, H. Mimura, S. Matsuyama, K. Yamauchi","doi":"10.1109/SOI.2010.5641395","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641395","url":null,"abstract":"An array of electrodes covering one-sixth of the area of an 8″ wafer was developed as a prototype system for NC sacrificial plasma oxidation. It was demonstrated that the system can be used for simultaneous NC processes by the individual control of the plasma-on time of each electrode.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133296782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Fernandes, R. Chapman, O. Seitz, H. Stiegler, H. Wen, Y. Chabal, E. Vogel
{"title":"Impact of back-gate biasing on ultra-thin silicon-on-insulator-based nanoribbon sensors","authors":"P. Fernandes, R. Chapman, O. Seitz, H. Stiegler, H. Wen, Y. Chabal, E. Vogel","doi":"10.1109/SOI.2010.5641066","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641066","url":null,"abstract":"In this study, we demonstrated that electrolytes in contact with SOI-based back-gated sensors are complexely coupled to applied back gate biases. Because to this, the liquid voltage modulates the top channel and controls the operating point of the device. This dual gating behavior has strong implications on the performance of both nanoribbon and nanowire sensors.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123497219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance characterization of PD-SOI ring oscillators at cryogenic temperatures","authors":"Igor V. Vernik, T. Ohki, M. Ketchen, M. Bhushan","doi":"10.1109/SOI.2010.5641394","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641394","url":null,"abstract":"We report on the successful operation of partially depleted silicon on insulator (PD-SOI) ring oscillators at temperatures down to 2.8 K. This 45 nm CMOS technology node hardware was fabricated on 300 mm wafers that were part of a development lot not optimized for low temperature operation. The test structure comprises a set of ring oscillators, an output multiplexer and a divide by 1024 circuit followed by an off-chip driver. By reducing the temperature of the device from 300 K to 2.8 K, the static power dissipation decreases by more than an order of magnitude. Circuit delays improve by approximately 20%, 16% from drive current enhancement and 4% from capacitance reduction. To gain further insight on this behavior we are measuring at cryogenic temperatures single MOSFETs and small arrays of MOSFETs that were fabricated alongside the ring oscillators. Experimental results and potential applications of cryogenic PD-SOI are presented.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126263745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Finishing of silicon film for silicon-on-glass","authors":"A. Usenko","doi":"10.1109/SOI.2010.5641053","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641053","url":null,"abstract":"Surface smoothing and removal of the damaged portion of as-transferred single crystalline silicon films is described. The process includes sacrificial plasma oxidation and wet stripping of the oxide. Typically, the topmost 20 nm of silicon film is removed in one cycle. Rougness of the film surface significantly improves upon the plasma/strip cycle. The process can be used for either SOI or silicon-on-glass (SiOG) finishing. As conventional CMP is not feasible for SiOG finishing, the described process has a unique advantage for finishing SiOG.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130202022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Ball, M. Alles, peixiong zhao, S. Cristoloveanu
{"title":"Comparing Single Event Upset sensitivity of bulk vs. SOI based FinFET SRAM cells using TCAD simulations","authors":"D. Ball, M. Alles, peixiong zhao, S. Cristoloveanu","doi":"10.1109/SOI.2010.5641058","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641058","url":null,"abstract":"The bulk and SOI FinFET SRAMs cells have comparable critical charges; however, the bulk cell has a lower upset LET threshold as well as larger sensitive cross section than the SOI cell. This implies a higher single event error rate in the bulk-based compared to SOI-based FinFET technologies.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127494820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Huang, R. Wang, J. Zhuge, T. Yu, Y. Ai, C. Fan, S. Pu, J. Zou, Y.Y. Wang
{"title":"Self-heating effect and characteristic variability of gate-all-around silicon nanowire transistors for highly-scaled CMOS technology (invited)","authors":"R. Huang, R. Wang, J. Zhuge, T. Yu, Y. Ai, C. Fan, S. Pu, J. Zou, Y.Y. Wang","doi":"10.1109/SOI.2010.5641472","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641472","url":null,"abstract":"This paper discusses self-heating effect and variability behavior of GAA SNWTs. Due to the 1-D nature of nanowire and increased phononboundary scattering in GAA structure, the selfheating effect in SNWTs based on bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus special design consideration is expected. On the other hand, random variation has become a practical problem at nano-scale. The characteristic variability of SNWTs is experimentally extracted and studied in detail. And the impacts of nanowire LER, the diameter-dependent annealing enhanced nanowire This paper discusses self-heating effect and variability behavior of GAA SNWTs. Due to the 1-D nature of nanowire and increased phononboundary scattering in GAA structure, the selfheating effect in SNWTs based on bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus special design consideration is expected. On the other hand, random variation has become a practical problem at nano-scale. The characteristic variability of SNWTs is experimentally extracted and studied in detail. And the impacts of nanowire LER, the diameter-dependent annealing enhanced nanowire","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134115905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Engineering a solution to jupiter exploration","authors":"K. Clark, T. Magner, M. Lisano, R. Pappalardo","doi":"10.1109/SOI.2010.5641049","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641049","url":null,"abstract":"The challenge associated with operating a spacecraft for long periods within the radiation belts of Jupiter is significant. The promise of incredible science is well worth the risk though, when the risk is identified and controlled. To be managed within reasonable resource limits, a system level engineering approach is needed to balance available resources, bolstering the weakest areas and adjusting the design as a whole for best results, rather than focusing on local concerns. It is important to establish these design methodologies early in conceptual development, and carry them forward in a committed, disciplined manner through development and operation. Early risk assessment and mitigation activities are also essential to controlling cost and risk. The JEO team has been pro-active in deploying a comprehensive risk mitigation plan, now in its second year, to retire most radiation risks prior to the Phase A development. The JPL/APL team has capitalized on prior deep space experience, significantly leveraging this technical expertise. Experience gained from Juno and RBSP would aid the proposed JEO mission during Phase A/B development; and the Galileo orbiter, in particular, has provided both a wealth of radiation data and an invaluable demonstration, well beyond anyone's expectations, of the practicability of operating a scientific spacecraft in the most intense regions of Jupiter's radiations belts.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129259676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evaluation of static noise margin and performance of 6T FinFET SRAM cells with asymmetric gate to source/drain underlap devices","authors":"V. Hu, M. Fan, P. Su, C. Chuang","doi":"10.1109/SOI.2010.5641392","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641392","url":null,"abstract":"This paper analyzes the stability, performance, and variability of 6T FinFET SRAM cells with asymmetric gate-to-source/drain underlap devices. At Vdd = 1V, using asymmetric source-underlap access transistors can improve RSNM while degrading WSNM; using source-underlap pull-up transistors can improve WSNM without sacrificing RSNM. Thus, the conflict between improving RSNM and WSNM in 6T FinFET SRAM cell can be relaxed by using the asymmetric source/drain underlap access and pull-up transistors (PUAX_Asym.). We also show, for the first time, that as Vdd is reduced (e.g. < 0.6V), the effectiveness of using asymmetric source/drain-underlap access transistors to improve RSNM diminishes due to the worse electrostatic integrity caused by the underlap. At Vdd = 1V, the 6T PUAX_Asym. SRAM cell shows 20.5% improvement in RSNM, comparable WSNM, 10% degradation in “cell” Read access time and 36% improvement in Time-to-Write compared with the conventional 6T SRAM cell (Symm.). The PUAX_Asym. SRAM cell also shows adequate μRSNM/sRSNM and μWSNM/σWSNM at Vdd = 1V.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115766914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}