Evaluation of static noise margin and performance of 6T FinFET SRAM cells with asymmetric gate to source/drain underlap devices

Abstract

This paper analyzes the stability, performance, and variability of 6T FinFET SRAM cells with asymmetric gate-to-source/drain underlap devices. At Vdd = 1V, using asymmetric source-underlap access transistors can improve RSNM while degrading WSNM; using source-underlap pull-up transistors can improve WSNM without sacrificing RSNM. Thus, the conflict between improving RSNM and WSNM in 6T FinFET SRAM cell can be relaxed by using the asymmetric source/drain underlap access and pull-up transistors (PUAX_Asym.). We also show, for the first time, that as Vdd is reduced (e.g. < 0.6V), the effectiveness of using asymmetric source/drain-underlap access transistors to improve RSNM diminishes due to the worse electrostatic integrity caused by the underlap. At Vdd = 1V, the 6T PUAX_Asym. SRAM cell shows 20.5% improvement in RSNM, comparable WSNM, 10% degradation in “cell” Read access time and 36% improvement in Time-to-Write compared with the conventional 6T SRAM cell (Symm.). The PUAX_Asym. SRAM cell also shows adequate μRSNM/sRSNM and μWSNM/σWSNM at Vdd = 1V.