P. Goyal, S. Gupta, R. Krishnan, W. Davies, H. Ho, A. Tessier, A. Arya, S. Deshpande, S. Fang, S. Lee, Z. Li, J. Liu, R. Takalkar, J. Dadson, A. Chakravarti, A. Domenicucci, J. Shepard, K. McStay, B. Morgenfeld, S. Allen, X. Li, B. Khan, R. Knarr, R. Arndt, R. Venigalla, P. Parries, M. Chudzik, S. Stiffler
{"title":"Characterization of novel TiN/HfO2 metal insulator semiconductor stack for 32nm eDRAM","authors":"P. Goyal, S. Gupta, R. Krishnan, W. Davies, H. Ho, A. Tessier, A. Arya, S. Deshpande, S. Fang, S. Lee, Z. Li, J. Liu, R. Takalkar, J. Dadson, A. Chakravarti, A. Domenicucci, J. Shepard, K. McStay, B. Morgenfeld, S. Allen, X. Li, B. Khan, R. Knarr, R. Arndt, R. Venigalla, P. Parries, M. Chudzik, S. Stiffler","doi":"10.1109/SOI.2010.5641378","DOIUrl":null,"url":null,"abstract":"In this paper, we describe the unique scaling challenges, critical sources of variation, and the potential trench leakage mechanisms of 32nm trench capacitors that utilize high-к/metal electrode materials. This is the first eDRAM technology that has successfully integrated high-к and metal films as part of the trench capacitor. In addition, these films are found to be fully compatible with front-end of line (FEOL) thermal budgets. We explore sources of variation and illustrate process mitigation techniques, including the targeting of key capacitor properties, and reduction in trench leakage. Finally, we illustrate that systematic and random variations do not pose as insurmountable barriers, and that the trench technology is scalable to the 22nm trench and beyond.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International SOI Conference (SOI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2010.5641378","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper, we describe the unique scaling challenges, critical sources of variation, and the potential trench leakage mechanisms of 32nm trench capacitors that utilize high-к/metal electrode materials. This is the first eDRAM technology that has successfully integrated high-к and metal films as part of the trench capacitor. In addition, these films are found to be fully compatible with front-end of line (FEOL) thermal budgets. We explore sources of variation and illustrate process mitigation techniques, including the targeting of key capacitor properties, and reduction in trench leakage. Finally, we illustrate that systematic and random variations do not pose as insurmountable barriers, and that the trench technology is scalable to the 22nm trench and beyond.
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