FDSOI metal gate transistors for ultra low power subthreshold operation

Abstract

A workfunction-tuned TiN metal gate is integrated into ultra-low-power FDSOI CMOS transistors, optimized for subthreshold operation at 0.3 V. The workfunction of the TiN metal gate is tunable across the mid-gap range, by adjusting deposition parameters and post-deposition annealing. The transistors show 71% reduction in Cgd and 55% reduction in Vt variation, compared to conventional FDSOI transistors of the same size. A 59% decrease in switching energy and a 91% decrease in stage delay is demonstrated in ring oscillators fabricated with the subthreshold-optimized FDSOI transistors when compared to commercial bulk silicon devices.