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2010 IEEE International SOI Conference (SOI)最新文献

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High performance and low variability fully-depleted strained-SOI MOSFETs 高性能和低可变性全耗尽应变soi mosfet
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641400
J. Mazurier, O. Weber, F. Andrieu, F. Allain, C. Tabone, A. Toffoli, C. Fenouillet-Béranger, L. Brevard, L. Tosti, P. Perreau, M. Belleville, O. Faynot
{"title":"High performance and low variability fully-depleted strained-SOI MOSFETs","authors":"J. Mazurier, O. Weber, F. Andrieu, F. Allain, C. Tabone, A. Toffoli, C. Fenouillet-Béranger, L. Brevard, L. Tosti, P. Perreau, M. Belleville, O. Faynot","doi":"10.1109/SOI.2010.5641400","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641400","url":null,"abstract":"In this paper, we demonstrate high performance Fully Depleted Silicon-On-Insulator CMOS on 300mm strained SOI (sSOI) wafers. Up to 100% drive current (ION) enhancement is demonstrated by sSOI nMOSFETs vs. unstrained SOI at W=80nm active width and L=45nm gate length. These devices indeed yield 1200µA/µm I<inf>ON</inf> at I<inf>OFF</inf>=10<sup>−8</sup> A/µm and V<inf>D</inf>=0.9V supply voltage. At the same time, they highlight the same excellent V<inf>T</inf> variability as the transistors on unstrained SOI. Optimizations of extensions and source/drain implants have been realized on both n&pMOS in order to boost further this trade-off between performance and variability thanks to electrostatic improvements.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"600 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116293805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
SOI-enabled three-dimensional integrated-circuit technology 基于soi的三维集成电路技术
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641367
C.K. Chen, B. Wheeler, D. Yost, J. Knecht, C. Chen, C. Keast
{"title":"SOI-enabled three-dimensional integrated-circuit technology","authors":"C.K. Chen, B. Wheeler, D. Yost, J. Knecht, C. Chen, C. Keast","doi":"10.1109/SOI.2010.5641367","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641367","url":null,"abstract":"We have demonstrated a new 3D device interconnect approach, with direct back side via connection to a transistor in a 3D stack, resulting in a reduced 3D footprint by an estimated ∼40% as well as potential for lower series resistance. We have demonstrated high yield 3D through-oxide-via (TOV) with a 40% size reduction to 1.0 µm and with an associated exclusion zone reduced by a factor of 2, substantially smaller than in bulk-Si 3D through-silicon-via (TSV) approaches. These significant enhancements were demonstrated with our 3D technology based on conventional SOI wafers.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131838092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Scaling floating-body DRAM: Rationale for a refined 2T Cell 缩放浮动体DRAM:改进2T Cell的基本原理
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641376
Zhichao Lu, Zhenming Zhou, J. Fossum
{"title":"Scaling floating-body DRAM: Rationale for a refined 2T Cell","authors":"Zhichao Lu, Zhenming Zhou, J. Fossum","doi":"10.1109/SOI.2010.5641376","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641376","url":null,"abstract":"SOI floating-body (1T) DRAM cells (FBCs) are of much interest today mainly because of integration problems associated with the storage capacitor of conventional 1T/1C DRAM in sub-50nm CMOS technology. Two fully depleted (FD) FBCs appear to have the best scaling potential: the planar thin-BOX FD/SOI MOSFET [1], and the quasi-planar double-gate (DG) FinFET [2]. We first examine, via 2-D and 3-D numerical simulations, the scalability of these 1T DRAM cells as implied by the memory margin and its dependence on the transistor body (UTB) thickness (tSi). Then, after showing and explaining significant margin losses in both devices as they are scaled to nanoscale gate lengths (Lg), we argue that better scalability is achievable in a 2T FBC, or floating-body/gate cell (FBGC), that we have previously presented [3], and we describe a novel refinement of the FBGC that yields very long charge/data retention times without undermining the good DRAM performance.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122300351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Non-planar device architecture for 15nm node: FinFET or trigate? 15nm节点的非平面器件架构:FinFET还是trigate?
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641060
Chung-Hsun Lin, Josephine B. Chang, M. Guillorn, A. Bryant, P. Oldiges, W. Haensch
{"title":"Non-planar device architecture for 15nm node: FinFET or trigate?","authors":"Chung-Hsun Lin, Josephine B. Chang, M. Guillorn, A. Bryant, P. Oldiges, W. Haensch","doi":"10.1109/SOI.2010.5641060","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641060","url":null,"abstract":"We have evaluated FinFET and Trigate performance under 15nm node ground rules. Trigate needs to maintain a high aspect ratio in order to achieve a comparable electrostatic performance of FinFET at tight FP, which makes it a fin-geometry instead of channel doping-controlled device. Trigate has less Cgs penalty compared to FinFET due to the additional current conduction at the top surface. The advantage of less parasitic capacitance will be reduced by other effects, such as parasitic resistance.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126947408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
High temperature RF behavior of SOI MOSFET transistors for low power low voltage applications 用于低功耗低电压应用的SOI MOSFET晶体管的高温射频行为
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641371
M. Emam, D. Vanhoenacker-Janvier, J. Raskin
{"title":"High temperature RF behavior of SOI MOSFET transistors for low power low voltage applications","authors":"M. Emam, D. Vanhoenacker-Janvier, J. Raskin","doi":"10.1109/SOI.2010.5641371","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641371","url":null,"abstract":"This paper presents a new approach to optimize the RF performance at high temperatures for low power low voltage applications. It is shown that the correct choice of the bias point can result in an improvement of the RF behavior of SOI transistors with increasing the temperature, which is opposite to the traditional degradation of RF behavior with increasing temperature. This approach is confirmed by RF measurements for both floating-body and body-tied SOI MOSFET transistors.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130274895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Novel characterization of fully-depleted GeOI pMOSFET by magnetoresistance 用磁电阻表征全耗尽GeOI pMOSFET的新方法
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641398
W. Van Den Daele, C. Le Royer, E. Augendre, G. Ghibaudo, S. Cristoloveanu
{"title":"Novel characterization of fully-depleted GeOI pMOSFET by magnetoresistance","authors":"W. Van Den Daele, C. Le Royer, E. Augendre, G. Ghibaudo, S. Cristoloveanu","doi":"10.1109/SOI.2010.5641398","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641398","url":null,"abstract":"Hole mobility in fully-depleted GeOI pMOSFETs is determined and analyzed using for the first time the geometric magnetoresistance technique. The temperature dependent measurements clarify the scattering mechanisms. A significant difference between effective mobility and magnetoresistance mobility is found. Unlike the SOI nMOSFET, this ratio (rMR ≃ 1.8) is rather independent on the temperature and inversion charge pointing out special scattering mechnisms.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121081275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical characterization of SOI solar cells in a wide temperature range SOI太阳能电池在宽温度范围内的电学特性
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641383
M. de Souza, O. Bulteel, D. Flandre, M. Pavanello
{"title":"Electrical characterization of SOI solar cells in a wide temperature range","authors":"M. de Souza, O. Bulteel, D. Flandre, M. Pavanello","doi":"10.1109/SOI.2010.5641383","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641383","url":null,"abstract":"In this work the influence of temperature on the characteristics of solar cells implemented in SOI substrate have been presented. It has been shown that the short-circuit current, open-circuit voltage and maximum power increase with temperature reduction. In addition, the fill factor improves at low temperatures, indicating that these solar cells may be succesfully used for space applications or other circuits designed to operate at cryogenic environments.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"18 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115626706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Extremely thin SOI (ETSOI) technology: Past, present, and future 极薄SOI (ETSOI)技术:过去、现在和未来
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641473
K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, J. Kuss, L. Edge, A. Kimball, S. Kanakasabapathy, S. Schmitz, A. Reznicek, T. Adam, H. He, S. Mehta, A. Upham, S. Seo, J. Herman, R. Johnson, Y. Zhu, P. Jamison, B. Haran, Z. Zhu, S. Fan, H. Bu, D. Sadana, P. Kozłowski, J. O’Neill, B. Doris, G. Shahidi
{"title":"Extremely thin SOI (ETSOI) technology: Past, present, and future","authors":"K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, J. Kuss, L. Edge, A. Kimball, S. Kanakasabapathy, S. Schmitz, A. Reznicek, T. Adam, H. He, S. Mehta, A. Upham, S. Seo, J. Herman, R. Johnson, Y. Zhu, P. Jamison, B. Haran, Z. Zhu, S. Fan, H. Bu, D. Sadana, P. Kozłowski, J. O’Neill, B. Doris, G. Shahidi","doi":"10.1109/SOI.2010.5641473","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641473","url":null,"abstract":"As the mainstream bulk devices face formidable challenges to scale beyond 20nm node, there is an increasingly renewed interest in fully depleted devices for continued CMOS scaling. In this paper, we provide an overview of extremely thin SOI (ETSOI), a viable fully depleted device architecture for future technology. Barriers that prevented ETSOI becoming a mainstream technology in the past are specified and solutions to overcome those barriers are provided.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115350244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Investigation of hysteresis memory effects in SOI FinFETs with ONO buried insulator ONO埋地绝缘子SOI finfet的磁滞记忆效应研究
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641374
S. Chang, K. Na, M. Bawedin, Y. Bae, K. Park, J. Lee, W. Xiong, S. Cristoloveanu
{"title":"Investigation of hysteresis memory effects in SOI FinFETs with ONO buried insulator","authors":"S. Chang, K. Na, M. Bawedin, Y. Bae, K. Park, J. Lee, W. Xiong, S. Cristoloveanu","doi":"10.1109/SOI.2010.5641374","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641374","url":null,"abstract":"Advanced FinFETs fabricated on SOI with ONO BOX are investigated for possible memory applications. Systematic measurements reveal the dynamics of BOX charging and discharging as a function of bias, dimensions, and time. The amount of charge trapped into the ONO dielectric is sensed, via 2D coupling, by the drain current. A strong hysteresis effect, potentially useful for non-volatile memory applications, is observed and discussed.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132411719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Development of self-assembled 3-D integration technology and study of microbump and TSV induced stress in thinned chip/wafer 自组装三维集成技术的发展及薄晶片微凸点和TSV诱导应力的研究
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641471
T. Tanaka, T. Fukushima, K. Lee, M. Murugesan, M. Koyanagi
{"title":"Development of self-assembled 3-D integration technology and study of microbump and TSV induced stress in thinned chip/wafer","authors":"T. Tanaka, T. Fukushima, K. Lee, M. Murugesan, M. Koyanagi","doi":"10.1109/SOI.2010.5641471","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641471","url":null,"abstract":"We have proposed and demonstrated the self-assembly technology that uses liquid surface tension to create a 3-D super-chip. Lots of chips can be simultaneously, precisely, and quickly aligned onto wafers with the self-assembly. We also studied the mechanical stress remained in the thinned Si chip/wafer using 2D micro-Raman spectroscopy. The measurement results pointed out that both metal micorbumps and TSVs induced the compressive and tensile stress in the thinned Si, and they might cause serious problems to 3-D LSIs. It is strongly required to remove the remaining stress in the thinnd Si chip/wafer.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123464766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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