Scaling floating-body DRAM: Rationale for a refined 2T Cell

Abstract

SOI floating-body (1T) DRAM cells (FBCs) are of much interest today mainly because of integration problems associated with the storage capacitor of conventional 1T/1C DRAM in sub-50nm CMOS technology. Two fully depleted (FD) FBCs appear to have the best scaling potential: the planar thin-BOX FD/SOI MOSFET [1], and the quasi-planar double-gate (DG) FinFET [2]. We first examine, via 2-D and 3-D numerical simulations, the scalability of these 1T DRAM cells as implied by the memory margin and its dependence on the transistor body (UTB) thickness (tSi). Then, after showing and explaining significant margin losses in both devices as they are scaled to nanoscale gate lengths (Lg), we argue that better scalability is achievable in a 2T FBC, or floating-body/gate cell (FBGC), that we have previously presented [3], and we describe a novel refinement of the FBGC that yields very long charge/data retention times without undermining the good DRAM performance.