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2010 IEEE International SOI Conference (SOI)最新文献

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Parasitic back-inferface conduction in planar and triple-gate SOI transistors 平面和三栅极SOI晶体管的寄生后界面传导
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641386
R. Ritzenthaler, F. Lime, M. Ricoma, F. Martinez, O. Faynot, F. Pascal, M. Valenza, E. Miranda, S. Cristoloveanu, B. Iñíguez
{"title":"Parasitic back-inferface conduction in planar and triple-gate SOI transistors","authors":"R. Ritzenthaler, F. Lime, M. Ricoma, F. Martinez, O. Faynot, F. Pascal, M. Valenza, E. Miranda, S. Cristoloveanu, B. Iñíguez","doi":"10.1109/SOI.2010.5641386","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641386","url":null,"abstract":"Using a compact model derived for long channels ΠFET, TGFETs and planar FDSOI transistors, it is demonstrated that experimental fully depleted devices can operate in the “back-interface inversion” regime even at VG2 grounded. As a result, two threshold voltages appear in the transistors, with an experimental difference of threshold voltages up to several hundreds mV for planar FDSOI devices. As a consequence, the back-interface channel is activated, leading to off-state current increase and subthreshold slope degradation. This effect can be alleviated by keeping a thick BOX when scaling down the structures, or by using vertical Multiple-GateFETs.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126724613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analysis of SOI MOSFET physics for compact modeling SOI MOSFET紧凑建模的物理分析
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641065
S. Baba, J. Ida, K. Tani, T. Chiba, Y. Igarashi, K. Sakamoto, M. Miura-Mattausch
{"title":"Analysis of SOI MOSFET physics for compact modeling","authors":"S. Baba, J. Ida, K. Tani, T. Chiba, Y. Igarashi, K. Sakamoto, M. Miura-Mattausch","doi":"10.1109/SOI.2010.5641065","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641065","url":null,"abstract":"This report shows an analysis of device operation on dynamic depletion mode of SOI MOSFETs, from view points of wide range geometry size, temperature and also considering device physics, second peak of gm, self-heating effect and so on. It is summarized a general picture of DD mode, which is important knowledge for next new compact circuit model.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114369968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Forward block characteristic of a novel RF SOI LDMOS with a buried P-type layer 一种新型埋p型层RF SOI LDMOS的正向阻挡特性
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641385
S. Xu, H.P. Zhang, D.J. Wang, G. H. Liu, X. Niu, M. Lin, L. Xu
{"title":"Forward block characteristic of a novel RF SOI LDMOS with a buried P-type layer","authors":"S. Xu, H.P. Zhang, D.J. Wang, G. H. Liu, X. Niu, M. Lin, L. Xu","doi":"10.1109/SOI.2010.5641385","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641385","url":null,"abstract":"A novel RF SOI LDMOS with buried P-type layer (BPL) was proposed for improvement of its forward block characteristic. The proposed BPL RF SOI LDMOS consists of an additional buried P-type layer inserted between buried oxide layer and N-drift region based on the conventional RF SOI LDMOS structure. When the proposed Device lies in forward block state, the junction across the interface between N-drift region and buried P-type layer is reverse biased, which bears the vertical forward voltage drop instead of thick BOX. It was proved by process and device simulations with Silvaco TCAD that the BPL RF SOI LDMOS is benefit not only to improve its breakdown voltage but also to thin buried oxide.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116090303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Stacked devices for SEU immune design 用于SEU免疫设计的堆叠器件
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641469
P. Oldiges, K. Rodbell, T. Ning, J. Cai, D. Heidel, H. Tang, L. Wissel, M. Gordon
{"title":"Stacked devices for SEU immune design","authors":"P. Oldiges, K. Rodbell, T. Ning, J. Cai, D. Heidel, H. Tang, L. Wissel, M. Gordon","doi":"10.1109/SOI.2010.5641469","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641469","url":null,"abstract":"A stacked transistor on SOI shows the potential to provide soft error upset immune designs. Key design elements are presented and analyzed showing tradeoffs between standard SOI devices and stacked devices, as well as alternative layouts to optimize soft error upset immunity.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114861239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design and evaluation of SOI devices for radiation environments 辐射环境下SOI器件的设计与评价
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641470
peixiong zhao, M. Alles, D. Fleetwood, D. Ball, M. Gadlage, F. El Mamouni
{"title":"Design and evaluation of SOI devices for radiation environments","authors":"peixiong zhao, M. Alles, D. Fleetwood, D. Ball, M. Gadlage, F. El Mamouni","doi":"10.1109/SOI.2010.5641470","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641470","url":null,"abstract":"SOI technologies offer key advantages for use in radiation environments, primarily related to reduced susceptibility to single-event effects. Because of charge trapping in the BOX, however, SOI technologies with light body doping (such as some fully depleted technologies) may be more sensitive to TID than similar bulk technologies. For sub 100-nm technologies, the advantages of SOI technologies related to SEE are less clear than they were in previous earlier technology generations because the critical charge required to upset the circuits is so low. The probability for upset (cross section), however, is lower for SOI circuits because charge collection does not occur over long distances, as it does in bulk technologies. This also reduces the likelihood that a single particle will affect multiple circuits in an IC.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116712103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Ultra-low dropout linear regulator using an SOI MESFET 采用SOI MESFET的超低差线性稳压器
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641384
W. Lepkowski, S. Wilk, B. Bakkaloglu, P. Fechner, T. Thornton
{"title":"Ultra-low dropout linear regulator using an SOI MESFET","authors":"W. Lepkowski, S. Wilk, B. Bakkaloglu, P. Fechner, T. Thornton","doi":"10.1109/SOI.2010.5641384","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641384","url":null,"abstract":"With these promising preliminary results, the next phase is to complete a fully integrated design similar to that in [1] on the 150nm SOI CMOS process. Ideally the performance will improve with respect to the transient responses and Ignd since the error amplifier can be optimally designed for the needs of the MESFET LDO.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"09 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127219195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
SOI CMOS technology for wireless applications: Current trends and perspectives 无线应用的SOI CMOS技术:当前趋势和前景
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641474
F. Gianesello, C. Raynaud, D. Gloria, B. Rauber
{"title":"SOI CMOS technology for wireless applications: Current trends and perspectives","authors":"F. Gianesello, C. Raynaud, D. Gloria, B. Rauber","doi":"10.1109/SOI.2010.5641474","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641474","url":null,"abstract":"During the past years, SOI technology has been widely adopted by our industry for the integration of RF front-end modules (FEMs), mainly for antenna switches. This paper reviews the current trends concerning the integration of FEM on CMOS SOI and discusses the perspectives for SOI technology to be used more widely by the wireless industry in a short future.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130367191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A metrology of silicon film thermal conductivity using micro-Raman spectroscopy 用微拉曼光谱测量硅膜导热系数
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641397
Xi Liu, Xiaoming Wu, T. Ren
{"title":"A metrology of silicon film thermal conductivity using micro-Raman spectroscopy","authors":"Xi Liu, Xiaoming Wu, T. Ren","doi":"10.1109/SOI.2010.5641397","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641397","url":null,"abstract":"We present a steady state technique enhanced with micro-Raman spectroscopy to measure thermal conductivity of SOI silicon device layer. This metrology, comparing to conventional technique based on thermistor, exhibits two improvements: robustness against ambient disturbance, which leads to an error of 28%, and reduction on measurement system error from 20% to 10%.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127966696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Reliability study in capacitor less 1T-RAM cells on SOI SOI上无电容1T-RAM电池可靠性研究
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641377
M. Aoulaiche, N. Collaert, E. Simoen, A. Mercha, B. de Wachter, K. Bourdelle, B. Nguyen, F. Boedt, D. Delprat, M. Jurczak, L. Altimime
{"title":"Reliability study in capacitor less 1T-RAM cells on SOI","authors":"M. Aoulaiche, N. Collaert, E. Simoen, A. Mercha, B. de Wachter, K. Bourdelle, B. Nguyen, F. Boedt, D. Delprat, M. Jurczak, L. Altimime","doi":"10.1109/SOI.2010.5641377","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641377","url":null,"abstract":"We have shown that careful optimization of the write conditions is needed in order to achieve the stringent endurance spec of 1016 cycles for 1T-RAM cells without compromising the sense margin and retention. The degradation seen during cycling of the cells can be attributed to the creation of interface states and carrier trapping at either the source (“0”) or drain side (“1”). Overall reduction of the biases, especially VD, will have a beneficial effect on the endurance behavior.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115899370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analog image processing circuit with 0.25µm CMOS compatible SOS MESFETs 模拟图像处理电路，0.25µm CMOS兼容SOS mesfet
2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI: 10.1109/SOI.2010.5641396
S. Kim, W. Lepkowski, T. Thornton, B. Bakkaloglu
{"title":"Analog image processing circuit with 0.25µm CMOS compatible SOS MESFETs","authors":"S. Kim, W. Lepkowski, T. Thornton, B. Bakkaloglu","doi":"10.1109/SOI.2010.5641396","DOIUrl":"https://doi.org/10.1109/SOI.2010.5641396","url":null,"abstract":"Image processing with Analog Neural Networks, performing horizontal line detection is demonstrated in a single poly, 3-layer metal digital CMOS technology utilizing SOS MESFET devices. Transient characteristics are measured by applying several combinations of grayscale input images. The measured transient response of the ANN array shows good agreement with simulations based on a TOM3 model extracted from the SOS MESFET. A worst case settling time of 4µs is achieved with the line detector.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116173429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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