SOI上无电容1T-RAM电池可靠性研究

2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI:10.1109/SOI.2010.5641377

M. Aoulaiche, N. Collaert, E. Simoen, A. Mercha, B. de Wachter, K. Bourdelle, B. Nguyen, F. Boedt, D. Delprat, M. Jurczak, L. Altimime

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引用次数: 0

摘要

我们已经表明，需要仔细优化写入条件，以便在不影响感知余量和保留的情况下实现1T-RAM单元1016周期的严格续航规格。在电池循环过程中看到的退化可归因于在源侧(“0”)或漏侧(“1”)产生界面状态和载流子捕获。总体上减少偏倚，特别是VD，将对耐力行为产生有益的影响。

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Reliability study in capacitor less 1T-RAM cells on SOI

We have shown that careful optimization of the write conditions is needed in order to achieve the stringent endurance spec of 1016 cycles for 1T-RAM cells without compromising the sense margin and retention. The degradation seen during cycling of the cells can be attributed to the creation of interface states and carrier trapping at either the source (“0”) or drain side (“1”). Overall reduction of the biases, especially VD, will have a beneficial effect on the endurance behavior.

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2010 IEEE International SOI Conference (SOI)

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