用于SEU免疫设计的堆叠器件

2010 IEEE International SOI Conference (SOI) Pub Date : 2010-11-18 DOI:10.1109/SOI.2010.5641469

P. Oldiges, K. Rodbell, T. Ning, J. Cai, D. Heidel, H. Tang, L. Wissel, M. Gordon

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引用次数: 7

摘要

在SOI上堆叠晶体管显示了提供软误差干扰免疫设计的潜力。提出并分析了关键设计元素，展示了标准SOI器件和堆叠器件之间的权衡，以及优化软错误干扰抗扰度的替代布局。

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Stacked devices for SEU immune design

A stacked transistor on SOI shows the potential to provide soft error upset immune designs. Key design elements are presented and analyzed showing tradeoffs between standard SOI devices and stacked devices, as well as alternative layouts to optimize soft error upset immunity.

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来源期刊

2010 IEEE International SOI Conference (SOI)

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