Parasitic back-inferface conduction in planar and triple-gate SOI transistors

Abstract

Using a compact model derived for long channels ΠFET, TGFETs and planar FDSOI transistors, it is demonstrated that experimental fully depleted devices can operate in the “back-interface inversion” regime even at VG2 grounded. As a result, two threshold voltages appear in the transistors, with an experimental difference of threshold voltages up to several hundreds mV for planar FDSOI devices. As a consequence, the back-interface channel is activated, leading to off-state current increase and subthreshold slope degradation. This effect can be alleviated by keeping a thick BOX when scaling down the structures, or by using vertical Multiple-GateFETs.