Development of self-assembled 3-D integration technology and study of microbump and TSV induced stress in thinned chip/wafer

Abstract

We have proposed and demonstrated the self-assembly technology that uses liquid surface tension to create a 3-D super-chip. Lots of chips can be simultaneously, precisely, and quickly aligned onto wafers with the self-assembly. We also studied the mechanical stress remained in the thinned Si chip/wafer using 2D micro-Raman spectroscopy. The measurement results pointed out that both metal micorbumps and TSVs induced the compressive and tensile stress in the thinned Si, and they might cause serious problems to 3-D LSIs. It is strongly required to remove the remaining stress in the thinnd Si chip/wafer.