J. Mazurier, O. Weber, F. Andrieu, F. Allain, C. Tabone, A. Toffoli, C. Fenouillet-Béranger, L. Brevard, L. Tosti, P. Perreau, M. Belleville, O. Faynot
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High performance and low variability fully-depleted strained-SOI MOSFETs
In this paper, we demonstrate high performance Fully Depleted Silicon-On-Insulator CMOS on 300mm strained SOI (sSOI) wafers. Up to 100% drive current (ION) enhancement is demonstrated by sSOI nMOSFETs vs. unstrained SOI at W=80nm active width and L=45nm gate length. These devices indeed yield 1200µA/µm ION at IOFF=10−8 A/µm and VD=0.9V supply voltage. At the same time, they highlight the same excellent VT variability as the transistors on unstrained SOI. Optimizations of extensions and source/drain implants have been realized on both n&pMOS in order to boost further this trade-off between performance and variability thanks to electrostatic improvements.
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