J. Popp, B. Kormanyos, M. Adams, A. Hurtado, J. Braatz, C. Wolfhausen, T. McKay
{"title":"45nm SOI CMOS毫米波混合信号电路设计","authors":"J. Popp, B. Kormanyos, M. Adams, A. Hurtado, J. Braatz, C. Wolfhausen, T. McKay","doi":"10.1109/SOI.2010.5641062","DOIUrl":null,"url":null,"abstract":"This work details the benefits of ultra deep submicron (UDSM) SOI CMOS technology for high performance mixed signal circuits at mm-wave frequencies. In particular, a mm-wave Direct Digital Synthesizer (DDS) design in 45nm partially depleted (PD) SOI CMOS is presented with post extraction simulated performance of 32 Gsps sample rate that rivals state of the art III–V DDS performance. Technology benefits of the 45nm PD-SOI technology's billion transistor integration, sub-5pS digital gate delays, and measured ∼400GHz ft/∼200GHz fmax cutoff frequency performance is highlighted. Increasing design challenges for UDSM CMOS mm-wave mixed signal circuits caused by increased gate leakage, limited transistor output impedance, inadequate foundry models, and required checking for design manufacturability are also addressed.","PeriodicalId":227302,"journal":{"name":"2010 IEEE International SOI Conference (SOI)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design of millimeter-wave mixed signal circuits in 45nm SOI CMOS\",\"authors\":\"J. Popp, B. Kormanyos, M. Adams, A. Hurtado, J. Braatz, C. Wolfhausen, T. McKay\",\"doi\":\"10.1109/SOI.2010.5641062\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work details the benefits of ultra deep submicron (UDSM) SOI CMOS technology for high performance mixed signal circuits at mm-wave frequencies. In particular, a mm-wave Direct Digital Synthesizer (DDS) design in 45nm partially depleted (PD) SOI CMOS is presented with post extraction simulated performance of 32 Gsps sample rate that rivals state of the art III–V DDS performance. Technology benefits of the 45nm PD-SOI technology's billion transistor integration, sub-5pS digital gate delays, and measured ∼400GHz ft/∼200GHz fmax cutoff frequency performance is highlighted. Increasing design challenges for UDSM CMOS mm-wave mixed signal circuits caused by increased gate leakage, limited transistor output impedance, inadequate foundry models, and required checking for design manufacturability are also addressed.\",\"PeriodicalId\":227302,\"journal\":{\"name\":\"2010 IEEE International SOI Conference (SOI)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International SOI Conference (SOI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.2010.5641062\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International SOI Conference (SOI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2010.5641062","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
这项工作详细介绍了超深亚微米(UDSM) SOI CMOS技术在毫米波频率下用于高性能混合信号电路的好处。特别是,提出了一种45nm部分耗尽(PD) SOI CMOS的毫米波直接数字合成器(DDS)设计,其提取后模拟性能为32 Gsps采样率,可与最先进的III-V DDS性能相媲美。45nm PD-SOI技术的技术优势包括十亿晶体管集成、低于5ps的数字门延迟以及测量的~ 400GHz ft/ ~ 200GHz fmax截止频率性能。UDSM CMOS毫米波混合信号电路的设计挑战日益增加,这些挑战包括栅极泄漏增加、晶体管输出阻抗有限、代工模型不充分以及需要对设计可制造性进行检查。
Design of millimeter-wave mixed signal circuits in 45nm SOI CMOS
This work details the benefits of ultra deep submicron (UDSM) SOI CMOS technology for high performance mixed signal circuits at mm-wave frequencies. In particular, a mm-wave Direct Digital Synthesizer (DDS) design in 45nm partially depleted (PD) SOI CMOS is presented with post extraction simulated performance of 32 Gsps sample rate that rivals state of the art III–V DDS performance. Technology benefits of the 45nm PD-SOI technology's billion transistor integration, sub-5pS digital gate delays, and measured ∼400GHz ft/∼200GHz fmax cutoff frequency performance is highlighted. Increasing design challenges for UDSM CMOS mm-wave mixed signal circuits caused by increased gate leakage, limited transistor output impedance, inadequate foundry models, and required checking for design manufacturability are also addressed.