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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)最新文献

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A 16 b quadrature direct digital frequency synthesizer using interpolative angle rotation algorithm 采用插值角度旋转算法的16b正交直接数字频率合成器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015069
Yongchul Song, Beomsup Kim
{"title":"A 16 b quadrature direct digital frequency synthesizer using interpolative angle rotation algorithm","authors":"Yongchul Song, Beomsup Kim","doi":"10.1109/VLSIC.2002.1015069","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015069","url":null,"abstract":"A quadrature direct digital frequency synthesizer (DDFS) is fabricated in 0.35 /spl mu/m CMOS using a new phase-to-sine conversion algorithm. It achieves a spurious-free dynamic range (SFDR) of 96 dB with small-sized lookup tables and appropriate arithmetic hardware. The prototype DDFS IC generates 16 b cosine and sine outputs with an output frequency tuning resolution of 0.03 Hz. It works at 150 MHz sampling rate, consuming 670 mW.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132746312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Programmable and automatically-adjustable sense-amplifier activation scheme and multi-reset address-driven decoding scheme for high-speed reusable SRAM core 高速可重复使用SRAM核心的可编程和自动可调感测放大器激活方案和多复位地址驱动解码方案
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015039
T. Suzuki, S. Nakahara, S. Iwahashi, K. Higeta, K. Kanetani, H. Nambu, M. Yoshida, K. Yamaguchi
{"title":"Programmable and automatically-adjustable sense-amplifier activation scheme and multi-reset address-driven decoding scheme for high-speed reusable SRAM core","authors":"T. Suzuki, S. Nakahara, S. Iwahashi, K. Higeta, K. Kanetani, H. Nambu, M. Yoshida, K. Yamaguchi","doi":"10.1109/VLSIC.2002.1015039","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015039","url":null,"abstract":"Describes novel schemes developed to meet the demand for a reusable embedded SRAM core for application to a variety of SOC designs. PAS optimizes sense-amplifier activation timing by using the combination of a program and automatic control. MRAD minimizes timing-overhead by reducing the fluctuation of path-to-path delay. These schemes experimentally demonstrated a wide-operation range of 0.5 to 1.4 V and an access time of 600 ps.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133249001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Ferroelectric-based functional pass-gate for low-power VLSI 基于铁电的低功耗VLSI功能通闸
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015082
H. Kimura, T. Hanyu, M. Kameyama, Y. Fujimori, T. Nakamura, H. Takasu
{"title":"Ferroelectric-based functional pass-gate for low-power VLSI","authors":"H. Kimura, T. Hanyu, M. Kameyama, Y. Fujimori, T. Nakamura, H. Takasu","doi":"10.1109/VLSIC.2002.1015082","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015082","url":null,"abstract":"A ferroelectric-based functional pass-gate is proposed for low-power logic-in-memory VLSI which makes communication bottlenecks free. Since non-destructive storage and switching functions are merged into a ferroelectric capacitor, active-device counts become small, which reduces the dynamic power dissipation. The use of ferroelectric-based non-volatile storage makes leakage currents cut off. Applying the ferroelectric-based circuitry to binary CAM implementation results in about half dynamic power reduction and 1/22000 static power reduction, compared to a. CMOS implementation under 0.6 /spl mu/m ferroelectric/CMOS.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122053622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Double boosting pump, hybrid current sense amplifier, and binary weighted temperature sensor adjustment schemes for 1.8V 128Mb mobile DRAMs 双升压泵，混合电流感测放大器，和二进制加权温度传感器调整方案1.8V 128Mb移动dram
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015108
J. Sim, H. Yoon, K. Chun, Hyun-Seok Lee, S. Hong, Soojeon Kim, Min-Soo Kim, Kyu-Chan Lee, Jei-Hwan Yoo, D.I. Seo, Sooin Cho
{"title":"Double boosting pump, hybrid current sense amplifier, and binary weighted temperature sensor adjustment schemes for 1.8V 128Mb mobile DRAMs","authors":"J. Sim, H. Yoon, K. Chun, Hyun-Seok Lee, S. Hong, Soojeon Kim, Min-Soo Kim, Kyu-Chan Lee, Jei-Hwan Yoo, D.I. Seo, Sooin Cho","doi":"10.1109/VLSIC.2002.1015108","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015108","url":null,"abstract":"A 1.8V 128Mb SDRAM is implemented for low current mobile applications with a 0.15/spl mu/m technology. The double boosting pump and hybrid current sense amplifier schemes are optimized for the low voltage regime with high pumping efficiency and stable I-to-V gain, respectively. A temperature sensor together with the binary weighted adjustment technique allow a very accurate implementation without loss in productivity.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127763348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A leakage-tolerant dynamic register file using leakage bypass with stack forcing (LBSF) and source follower NMOS (SFN) techniques 一种采用堆栈强制泄漏旁路(LBSF)和源跟随器NMOS (SFN)技术的容漏动态寄存器文件
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015115
S. Tang, S. Hsu, Y. Ye, J. Tschanz, D. Somasekhar, S. Narendra, Shih-Lien Lu, R. Krishnamurthy, V. De
{"title":"A leakage-tolerant dynamic register file using leakage bypass with stack forcing (LBSF) and source follower NMOS (SFN) techniques","authors":"S. Tang, S. Hsu, Y. Ye, J. Tschanz, D. Somasekhar, S. Narendra, Shih-Lien Lu, R. Krishnamurthy, V. De","doi":"10.1109/VLSIC.2002.1015115","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015115","url":null,"abstract":"Clock frequency of a multi-ported, 256/spl times/32b dynamic register file in a 100nm technology is improved by 50%, compared to the best dual-V/sub T/ (DVT) design, using LBSF and SFN leakage-tolerant circuit techniques for LBL and GBL. Total transistor width of the full LBSF design is the smallest.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121112754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
1-Gb/s/pin multi-gigabit DRAM design with low impedance hierarchical I/O architecture 1 gb /s/引脚多千兆DRAM设计，具有低阻抗分层I/O架构
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015061
H. Fujisawa, T. Takahashi, H. Yoko, I. Fujii, Y. Takai, M. Nakamura
{"title":"1-Gb/s/pin multi-gigabit DRAM design with low impedance hierarchical I/O architecture","authors":"H. Fujisawa, T. Takahashi, H. Yoko, I. Fujii, Y. Takai, M. Nakamura","doi":"10.1109/VLSIC.2002.1015061","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015061","url":null,"abstract":"A low impedance hierarchical I/O architecture designed to realize both high-speed and low-voltage DRAMs is presented. In this architecture, use of the divided I/O lines over the memory cells reduces the load of I/O lines by 50% and enables a 2.2 ns reduction of the read/write cycle time. By combining the distributed data transfer scheme, we achieved a 4 ns reduction of the access time to 8 ns and 1-Gb/s/pin operation with a 1.8-V power supply in a multi-Gb DRAM.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131607564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
1.2 Gbps/pin simultaneous bidirectional transceiver logic with bit deskew technique 1.2 Gbps/pin同时双向收发逻辑与位倾斜技术
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015044
Y. Fujimura, T. Takahashi, S. Toyoshima, K. Nagashima, J. Baba, T. Matsumoto
{"title":"1.2 Gbps/pin simultaneous bidirectional transceiver logic with bit deskew technique","authors":"Y. Fujimura, T. Takahashi, S. Toyoshima, K. Nagashima, J. Baba, T. Matsumoto","doi":"10.1109/VLSIC.2002.1015044","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015044","url":null,"abstract":"We have developed a simultaneous bidirectional transceiver logic -composed of a transmitter with an output level feedback pre-buffer and a receiver with two sense amplifiers and a hazard-free selector - that reduces the data jitter originating from three voltage level transmission. We also developed a bit deskew technique that takes into account the influence of switching noise to obtain the maximum timing margin in multi-pin operation. Stable throughput of 1.2 Gbps/pin was achieved in simultaneous 81-pin operation using a printed circuit board.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132352589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
SOI-optimized 64-bit high-speed CMOS adder design soi优化的64位高速CMOS加法器设计
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015062
Jae-Joon Kim, R. Joshi, C. Chuang, K. Roy
{"title":"SOI-optimized 64-bit high-speed CMOS adder design","authors":"Jae-Joon Kim, R. Joshi, C. Chuang, K. Roy","doi":"10.1109/VLSIC.2002.1015062","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015062","url":null,"abstract":"Presents a high-speed 64-bit hybrid carry-lookahead/carry-select adder in 0.1 /spl mu/m partially depleted silicon-on-insulator (PD/SOI) technology with a critical path delay of 346 ps. Sense-amplifier based differential logic with source follower evaluation tree is used for fast generation of 8-bit group carry. Floating body PD/SOI shows 24% performance improvement over bulk CMOS for the 8-bit group carry generating circuit. We also show that the proposed circuit is robust to noise induced by floating body effect in PD/SOI.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127202484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An on-chip high-efficiency DC-DC converter with a compact timing edge control circuit 片上高效率DC-DC转换器，具有紧凑的定时边缘控制电路
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015104
Ton Ogawa, S. Hatanaka, Kenji Taniguchi
{"title":"An on-chip high-efficiency DC-DC converter with a compact timing edge control circuit","authors":"Ton Ogawa, S. Hatanaka, Kenji Taniguchi","doi":"10.1109/VLSIC.2002.1015104","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015104","url":null,"abstract":"We developed an on-chip DC-DC converter with a compact timing edge control circuit operating at high clock frequency. The circuit generates four states to control nearly ideal switchings of output transistors depending on the voltages sensed at two terminals across an off-chip output inductor. High efficiency can be achieved due to nearly exact timing edge control with the aid of a high frequency clock by eliminating the conventional dead time control circuit. The DC-DC converter is fabricated in 0.25 /spl mu/m CMOS process with single polysilicon and triple metal. The experimental results at 2.5 V output show efficiency over 90% with a off-chip filter consisting of a inductor of 220 /spl mu/H and a ceramic capacitor of 47 /spl mu/F. The converter has maximum efficiency of 93.3% with 29 mV ripple at 37 mA load current.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116925292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
High efficiency and latch-up free switched capacitor up converter on FD-SOI technology 基于FD-SOI技术的高效率无锁存开关电容上变频器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015107
J. Kajiwara, M. Kinoshita, S. Sakiyama, A. Matsuzawa
{"title":"High efficiency and latch-up free switched capacitor up converter on FD-SOI technology","authors":"J. Kajiwara, M. Kinoshita, S. Sakiyama, A. Matsuzawa","doi":"10.1109/VLSIC.2002.1015107","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015107","url":null,"abstract":"We have developed a latch-up free Switched Capacitor (SC) type voltage up converter on 0.35 /spl mu/m FD-SOI technology. In this paper, we propose approximate theoretic expressions of the power efficiency and the output voltage. A test chip confirms the validity of these theoretic expressions. As a result, we can optimize the performances for various load currents of the up converter. The up converter achieved a power conversion efficiency of 93.5% including self-power. consumption at 1 mA DC load current, where switching frequency is 100 kHz, input voltage is 0.8 V, V out is 1.55 V, and capacitance is 10 /spl mu/F.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115165492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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