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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)最新文献

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Static pulsed bus for on-chip interconnects 用于片上互连的静态脉冲总线
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015051
M. Khellah, J. Tschanz, Y. Ye, S. Narendra, V. De
{"title":"Static pulsed bus for on-chip interconnects","authors":"M. Khellah, J. Tschanz, Y. Ye, S. Narendra, V. De","doi":"10.1109/VLSIC.2002.1015051","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015051","url":null,"abstract":"Static Pulsed Bus (SPB) improves delay by 15%-25% or reduces energy by 12%-25% and peak current by 26%-34%, compared to the conventional static bus (SB) scheme, for 1500 μm to 4500 μm bus lengths in a 100 nm technology. Energy savings are maintained across all data activity factors.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126827355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Design rule for frequency-voltage cooperative power control and its application to an MPEG-4 decoder 频率-电压协同功率控制设计规则及其在MPEG-4解码器中的应用
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015088
Kazuo Aisaka, Toshiyuki Aritsuka, Satoshi Misaka, Keisuke Toyama, Kunio Uchiyama, K. Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai
{"title":"Design rule for frequency-voltage cooperative power control and its application to an MPEG-4 decoder","authors":"Kazuo Aisaka, Toshiyuki Aritsuka, Satoshi Misaka, Keisuke Toyama, Kunio Uchiyama, K. Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai","doi":"10.1109/VLSIC.2002.1015088","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015088","url":null,"abstract":"Frequency-voltage cooperative power control (FVC) is considered a powerful method to reduce the power consumption of a program, because it utilizes the information of software loads dynamically. The authors first show through a mathematical analysis that FVC with only two frequency-voltage sets is sufficient for current low-Vdd CPU chips. Then we show an experimental result that FVC feedback control on an MPEG-4 video decoder can reduce the power to one-fourth.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121776239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A robust array architecture for a capacitorless MISS tunnel-diode memory 一种用于无电容MISS隧道二极管存储器的鲁棒阵列结构
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015070
S. Hanzawa, T. Sakata, T. Sekiguchi, H. Matsuoka
{"title":"A robust array architecture for a capacitorless MISS tunnel-diode memory","authors":"S. Hanzawa, T. Sakata, T. Sekiguchi, H. Matsuoka","doi":"10.1109/VLSIC.2002.1015070","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015070","url":null,"abstract":"With the aim of applying a MISS tunnel-diode cell to a high-density RAM, we studied its problems and developed three circuit techniques to solve them. The first, a hierarchical bit-line structure increases the number of memory cells in a bit-line and reduces the number of sense amplifiers. The second, a twin-dummy-cell technique generates a proper reference signal to discriminate read currents. The third, a standby-voltage control scheme reduces background currents and suppresses the degeneration of the signal current. These techniques enable a high-density RAM to use the capacitorless MISS-diode memory cell, whose effective cell area is 6F/sup 2/ (F: minimum feature size). The third technique increases the signal current from 0.25 to 0.85 compared to the original one.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123178714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Threshold-voltage balance for minimum supply operation 最小供电运行的阈值电压平衡
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015085
G. Ono, Masayulu Miyazaki
{"title":"Threshold-voltage balance for minimum supply operation","authors":"G. Ono, Masayulu Miyazaki","doi":"10.1109/VLSIC.2002.1015085","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015085","url":null,"abstract":"The difference between the threshold voltages (Vt) of PMOS and NMOS transistor is a critical issue in the operation of low voltage circuits. The P/N Vt balancing profit is analyzed in terms of sub-threshold leakage current, minimum supply voltage, and static noise margin. Balancing the P/N Vt reduces the lowest required supply voltage by 0.15-0.3 V. The use of our proposed Vt matching scheme enables CMOS LSI minimum supply voltage processing at 0.1 V.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131321603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A 6bit 400Msps 70mW ADC using interpolated parallel scheme 采用内插并行方案的6bit 400Msps 70mW ADC
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015116
K. Ono, H. Shimizu, J. Ogawa, M. Takeda, M. Yano
{"title":"A 6bit 400Msps 70mW ADC using interpolated parallel scheme","authors":"K. Ono, H. Shimizu, J. Ogawa, M. Takeda, M. Yano","doi":"10.1109/VLSIC.2002.1015116","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015116","url":null,"abstract":"The design of a low power 6bit, 400Msps, 1.8V CMOS ADC is presented. This ADC is based on interpolated parallel architecture in which the transistor sizes are optimized to achieve the required linearity and simultaneously minimize the power consumption. When operated at 400Msps with 1.8/2.4V power supply the ADC dissipates 70mW. The ADC is fabricated in a 0.18/spl mu/m CMOS process.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126283487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 380-MHz CMOS linear-in-dB signal-summing variable gain amplifier with gain compensation techniques for CDMA systems 采用增益补偿技术的380 mhz CMOS db信号加和可变增益放大器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015066
O. Watanabe, S. Otaka, M. Ashida, T. Itakura
{"title":"A 380-MHz CMOS linear-in-dB signal-summing variable gain amplifier with gain compensation techniques for CDMA systems","authors":"O. Watanabe, S. Otaka, M. Ashida, T. Itakura","doi":"10.1109/VLSIC.2002.1015066","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015066","url":null,"abstract":"A linear-in-dB signal-summing Variable Gain Amplifier (VGA) is fabricated in 0.25 /spl mu/m CMOS technology. Two gain compensation techniques are proposed in order to compensate the gain deviations due to the MOSFET characteristic which has a square-law characteristic or an exponential-law characteristic determined by its current density. Temperature compensation techniques are also proposed. A gain range of 80 dB, a gain error of within /spl plusmn/3 dB, an NF of 11 dB are obtained at 380 MHz by measurement.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133859896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Wireless implantable microsystems: coming breakthroughs in health care 无线植入式微系统:医疗保健领域即将取得突破
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015057
K. Wise
{"title":"Wireless implantable microsystems: coming breakthroughs in health care","authors":"K. Wise","doi":"10.1109/VLSIC.2002.1015057","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015057","url":null,"abstract":"This paper reviews recent progress in implantable microsystems. Electrode arrays of up to 1024 sites now allow direct interfacing with the central nervous system, monitoring neural activity and delivering both electrical and chemical stimulation. Operating at milliwatt levels with site spacings of 100-400 /spl mu/m and communicating wirelessly at up to 100 kb/s, these arrays form a microelectronic bridge to the cellular world. Combined with embedded processors and wafer-level packaging, these microsystems promise exciting advances in dealing with a variety of neurological disorders during the coming decade.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133514802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A 4th-order local-feedforward D/A converter that prevents limit-cycle oscillation 一种防止限环振荡的四阶本地前馈D/A转换器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015119
Y. Matsuya, Y. Kado, J. Terada, T. Eguchi, M. Tamura, H. Fujiwara
{"title":"A 4th-order local-feedforward D/A converter that prevents limit-cycle oscillation","authors":"Y. Matsuya, Y. Kado, J. Terada, T. Eguchi, M. Tamura, H. Fujiwara","doi":"10.1109/VLSIC.2002.1015119","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015119","url":null,"abstract":"Limit-cycle oscillation in noise-shaping D/A converters is one of serious problems because it interrupts their noise-shaping operation. We propose a new noise-shaping structure that prevents limit-cycle oscillation. We have used this structure in an audio D/A converter that we fabricated. The measured result shows that limit-cycle oscillation is prevented and noise-shaping operation is maintained even when the input data is real zero. This D/A converter achieves the S/N+THD of 101 dB.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"69 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114034674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The evolution of monolithic and polylithic interconnect technology 单片和多片互连技术的发展
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015027
James D. Meindl
{"title":"The evolution of monolithic and polylithic interconnect technology","authors":"James D. Meindl","doi":"10.1109/VLSIC.2002.1015027","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015027","url":null,"abstract":"Monolithic interconnect technology has evolved rapidly over the past four decades in order to keep pace with advances in transistor density and performance. Optimal reverse scaling, integrated architectures for global signal, power and clock distribution networks of a heterogeneous system-on-a-chip, 3D integration and microphotonic interconnects offer promising approaches to satisfy future stringent monolithic interconnect requirements of GSI. Polylithic integration featuring batch processing of high density chip input/output interconnects and high density printed wiring board interconnects is projected as an increasingly important feature of future gigascale microsystems.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132134087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
1.5 Gbps, 5150 ppm spread spectrum SerDes PHY with a 0.3 mW, 1.5 Gbps level detector for serial ATA 1.5 Gbps, 5150 ppm扩频SerDes PHY，带有用于串行ATA的0.3 mW, 1.5 Gbps电平检测器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015045
M. Sugawara, K. Ogasawara, M. Aoyama, M. Zwerg, S. Głowiński, Y. Kameyama, T. Yanagita, M. Fukaishi, S. Shimoyama, T. Ishibashi, T. Noma
{"title":"1.5 Gbps, 5150 ppm spread spectrum SerDes PHY with a 0.3 mW, 1.5 Gbps level detector for serial ATA","authors":"M. Sugawara, K. Ogasawara, M. Aoyama, M. Zwerg, S. Głowiński, Y. Kameyama, T. Yanagita, M. Fukaishi, S. Shimoyama, T. Ishibashi, T. Noma","doi":"10.1109/VLSIC.2002.1015045","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015045","url":null,"abstract":"We have successfully developed a 5150 ppm spread spectrum serializer/deserializer (SerDes) physical layer (PHY) chip compliant with the serial AT attachment (ATA), The device was fabricated by a 0.13 /spl mu/m, 1.5 V CMOS process and includes a self-running, pulse-swallow phase locked loop (PLL) to generate the transmit (TX) carrier, a triple loop tracking the PLL to recover the receive (RX) clock, and a 0.3 mW current-crossover level detector to detect the 1.5 Gbps carrier for initial communication.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134539182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
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