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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)最新文献

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Power dissipation issues in interconnect performance optimization for sub-180 nm designs 亚180nm互连性能优化中的功耗问题
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015029
K. Banerjee, A. Mehrotra
{"title":"Power dissipation issues in interconnect performance optimization for sub-180 nm designs","authors":"K. Banerjee, A. Mehrotra","doi":"10.1109/VLSIC.2002.1015029","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015029","url":null,"abstract":"This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and inter-buffer interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty. Furthermore, this technique is also used to quantify the relative importance of the various components of the power dissipation for power-optimal solutions for various technology nodes.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133489308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs 采用片上调节双环锁相环的0.4- 4gb /s CMOS四路收发器单元
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015054
Ken-Hao Chang, Jason Wei, Charlie Huang, S. Li, K. Donnelly, M. Horowitz, Yingxuan Li, S. Sidiropoulos
{"title":"A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs","authors":"Ken-Hao Chang, Jason Wei, Charlie Huang, S. Li, K. Donnelly, M. Horowitz, Yingxuan Li, S. Sidiropoulos","doi":"10.1109/VLSIC.2002.1015054","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015054","url":null,"abstract":"A quad high-speed transceiver cell is designed and implemented in 0.13 /spl mu/m CMOS technology. To achieve low jitter while maintaining low power consumption, dual on-chip regulators are used for each dual-loop PLL. The prototype chip demonstrates that the links can operate from 400 Mb/s to 4 Gb/s with a bit error rate <10/sup -14/. The quad cell consumes 390 mW at 2.5 Gb/s (95 mW/link) under typical operating conditions with a 400 mV output swing driving double terminated links.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116587379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 93
A 1.8-V operation RFCMOS transceiver for Bluetooth 用于蓝牙的1.8 v操作RFCMOS收发器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015092
H. Komurasaki, T. Heima, T. Miwa, K. Yamamoto, H. Wakada, I. Yasui, M. Ono, T. Sano, H. Sato, T. Miki, N. Kato
{"title":"A 1.8-V operation RFCMOS transceiver for Bluetooth","authors":"H. Komurasaki, T. Heima, T. Miwa, K. Yamamoto, H. Wakada, I. Yasui, M. Ono, T. Sano, H. Sato, T. Miki, N. Kato","doi":"10.1109/VLSIC.2002.1015092","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015092","url":null,"abstract":"This paper describes a single-chip Bluetooth transceiver LSI, which uses a standard 0.18 /spl mu/m bulk CMOS process. It can operate at a supply voltage of 1.8 V, and includes even a low loss transmit/receive antenna switch (SW) in order to realize high level integration. For lower chip area, a channel selection filter consists of simple linearized source-coupled pairs, and the transceiver occupies 10.2 mm/sup 2/.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130901583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 125 MHz-86 dB IM3 programmable-gain amplifier 一个125 MHz-86 dB的IM3可编程增益放大器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015035
Cheng-Chung Hsu, Jieh-Tsorng Wu
{"title":"A 125 MHz-86 dB IM3 programmable-gain amplifier","authors":"Cheng-Chung Hsu, Jieh-Tsorng Wu","doi":"10.1109/VLSIC.2002.1015035","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015035","url":null,"abstract":"A digitally programmable-gain amplifier (PGA) is realized using a 0.35 /spl mu/m CMOS technology. Constant bandwidth and high linearity are achieved by using a current-mode amplifier with resistor-network feedback. The PGA has a voltage gain varying from 0 dB to 19 dB with a bandwidth of 125 MHz. With 1 Vpp output, the third-order intermodulation (IM3) of the PGA is -86 dB at 10 MHz and -59 dB at 80 MHz. The distortion is also insensitive to the gain change. The circuit dissipates 21 mW from a 3.3 V supply.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122183445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Selective node engineering for chip-level soft error rate improvement [in CMOS] 芯片级软错误率改进的选择性节点工程[在CMOS中]
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015084
T. Karnik, S. Vangal, V. Veeramachaneni, P. Hazucha, V. Erraguntla, S. Borkar
{"title":"Selective node engineering for chip-level soft error rate improvement [in CMOS]","authors":"T. Karnik, S. Vangal, V. Veeramachaneni, P. Hazucha, V. Erraguntla, S. Borkar","doi":"10.1109/VLSIC.2002.1015084","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015084","url":null,"abstract":"This paper presents a technique to selectively engineer sequential or domino nodes in high performance circuits to improve soft error rate (SER) induced by cosmic rays or alpha particles. In 0.18 /spl mu/m process, the SER improvement is as much as 3/spl times/ at the cell-level, 1.8/spl times/ at the block-level and 1.3/spl times/ at the chip-level without any penalty in performance or area, and <3% power penalty. The node selection, hardening and SER quantification steps are fully automated.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124168228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 78
A binocular CMOS range image sensor with bit-serial block-parallel interface using cyclic pipelined ADCs 一种采用循环流水线adc的位串行块并行接口的双目CMOS距离图像传感器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015102
T. Kato, S. Kawahito, K. Kobayashi, H. Sasaki, T. Eki, T. Hisanaga
{"title":"A binocular CMOS range image sensor with bit-serial block-parallel interface using cyclic pipelined ADCs","authors":"T. Kato, S. Kawahito, K. Kobayashi, H. Sasaki, T. Eki, T. Hisanaga","doi":"10.1109/VLSIC.2002.1015102","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015102","url":null,"abstract":"A binocular CMOS image sensor used with a pair of aligned-in-parallel optical systems for range imaging is implemented. Sixteen compact cyclic pipelined analog-to-digital converters are integrated per an image sensor. The dedicated processor starts 16/spl times/16 FFT when the first bit-serial block-parallel data is obtained. The image sensor produces a 16/spl times/16 range image from a pair of 256/spl times/256 images, together with the dedicated pipelined FFT processor, at the maximum pipeline performance.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121488779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A transition-encoded dynamic bus technique for high-performance interconnects 用于高性能互连的转换编码动态总线技术
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015031
M. Anders, N. Rai, R. Krishnamurthy, S. Borkar
{"title":"A transition-encoded dynamic bus technique for high-performance interconnects","authors":"M. Anders, N. Rai, R. Krishnamurthy, S. Borkar","doi":"10.1109/VLSIC.2002.1015031","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015031","url":null,"abstract":"A transition-encoded dynamic bus technique enables interconnect delay reduction while maintaining the robustness and switching energy behavior of a static bus. Efficient circuits, designed for a drop-in replacement, enable significant delay and peak-current reduction even for short buses, while obtaining energy savings at aggressive delay targets. In a 180 nm 32-bit microprocessor, 79% of all global buses exhibit 10%-35% performance improvement with this technique.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132600966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
High performance SRAMs in 1.5 V, 0.18 /spl mu/m partially depleted SOI technology 采用1.5 V, 0.18 /spl mu/m部分耗尽SOI技术的高性能sram
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015050
R. Joshi, A. Pellela, O. Wagner, Y. Chan, W. Dachtera, S. Wilson, S. Kowalczyk
{"title":"High performance SRAMs in 1.5 V, 0.18 /spl mu/m partially depleted SOI technology","authors":"R. Joshi, A. Pellela, O. Wagner, Y. Chan, W. Dachtera, S. Wilson, S. Kowalczyk","doi":"10.1109/VLSIC.2002.1015050","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015050","url":null,"abstract":"This paper describes high speed SRAMs with read access time below 500 ps and a cycle time around 2 GHz in 1.5 V, 0.18 /spl mu/m partially depleted (PD) SOI CMOS technology. The paper also provides the robust designs to improve performance and functionality in PD SOI. The highlights of the paper are optimized timing for pseudostatic circuits, novel design of the sense amplifier, design techniques to improve functionality and performance at high temperatures and cell stability. Also a full functional SRAM (Directory, L1 Cache and other SRAMs) hardware with high yields is demonstrated by providing extensive test pattern coverage generated by a programmable \"Array-Built-In-Self-Test\" (ABIST).","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131232005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects 基于1T1MTJ位单元集成铜互连的低功耗1mbit MRAM
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015073
M. Durlam, P. Naji, A. Omair, M. Deherrera, J. Calder, J. Slaughter, B. Engel, N. Rizzo, G. Grynkewich, B. Butcher, C. Tracy, K. Smith, K. Kyler, J. Ren, J. Molla, B. Feil, R. Williams, S. Tehrani
{"title":"A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects","authors":"M. Durlam, P. Naji, A. Omair, M. Deherrera, J. Calder, J. Slaughter, B. Engel, N. Rizzo, G. Grynkewich, B. Butcher, C. Tracy, K. Smith, K. Kyler, J. Ren, J. Molla, B. Feil, R. Williams, S. Tehrani","doi":"10.1109/VLSIC.2002.1015073","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015073","url":null,"abstract":"A low power 1 Mb Magnetoresistive Random Access Memory (MRAM) based on a 1-Transistor and 1-Magnetic Tunnel Junction (1T1MTJ) bit cell is demonstrated. This is the largest MRAM memory demonstration to date. In this circuit, MTJ elements are integrated with CMOS using copper interconnect technology. The copper interconnects are cladded with a high permeability layer which is used to focus magnetic flux generated by current flowing through the lines toward the MTJ devices and reduce the power needed for programming the bits. The 25 mm/sup 2/ 1 Mb MRAM circuit operates with address access times of less than 50 ns, consuming 24 mW at 3.0 V and 20 MHz. The circuit is fabricated in a 0.6 /spl mu/m CMOS process utilizing five layers of metal and two layers of poly.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114351211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
A monolithic CMOS 10.4-GHz phase locked loop 单片CMOS 10.4 ghz锁相环
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015037
Dong-Jun Yang, K. O
{"title":"A monolithic CMOS 10.4-GHz phase locked loop","authors":"Dong-Jun Yang, K. O","doi":"10.1109/VLSIC.2002.1015037","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015037","url":null,"abstract":"A 10.4-GHz PLL with a 256/257 dual modulus prescaler implemented in a 0.18-/spl mu/m CMOS process is presented. The prescaler with a 4/5 synchronous counter operates up to 14 GHz. The counter achieves this by using feedback. The phase noise levels of the PLL and VCO at a 3-MHz offset with I/sub VCO/=8.1 mA are -122 dBc/Hz. The PLL operates between 9.7 10.4 GHz, while drawing 34 mA at V/sub DD/=1.8 V.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115740002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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