High performance SRAMs in 1.5 V, 0.18 /spl mu/m partially depleted SOI technology

Abstract

This paper describes high speed SRAMs with read access time below 500 ps and a cycle time around 2 GHz in 1.5 V, 0.18 /spl mu/m partially depleted (PD) SOI CMOS technology. The paper also provides the robust designs to improve performance and functionality in PD SOI. The highlights of the paper are optimized timing for pseudostatic circuits, novel design of the sense amplifier, design techniques to improve functionality and performance at high temperatures and cell stability. Also a full functional SRAM (Directory, L1 Cache and other SRAMs) hardware with high yields is demonstrated by providing extensive test pattern coverage generated by a programmable "Array-Built-In-Self-Test" (ABIST).