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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)最新文献

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0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array-voltage scheme 采用矩形扩散单元和增量阵列电压方案的0.4 v逻辑库友好SRAM阵列
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015076
M. Yamaoka, K. Osada, K. Ishibashi
{"title":"0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array-voltage scheme","authors":"M. Yamaoka, K. Osada, K. Ishibashi","doi":"10.1109/VLSIC.2002.1015076","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015076","url":null,"abstract":"We designed a logic library friendly SRAM array. The array uses rectangular-diffusion cell (RD-cell) and delta-boosted-array-voltage scheme (DBA-scheme). In the RD-cell, the cell ratio is 1.0, and it reduces the imbalance of the cell ratio. A low supply voltage deteriorates the static noise margin, however, the DBA-scheme compensates it. Using the combination of RD-cell and DBA-scheme, a 32-kB test chip achieves 0.4-V operation at 4.5-MHz frequency and 140-/spl mu/W power dissipation and 0.9-/spl mu/A standby current.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123430901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Constant-charge-injection programming for 10-MB/s multilevel AG-AND flash memories 用于10mb /s多级ag和闪存的恒定电荷注入编程
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015110
H. Kurata, S. Saeki, T. Kobayashi, Y. Sasago, T. Kawahara
{"title":"Constant-charge-injection programming for 10-MB/s multilevel AG-AND flash memories","authors":"H. Kurata, S. Saeki, T. Kobayashi, Y. Sasago, T. Kawahara","doi":"10.1109/VLSIC.2002.1015110","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015110","url":null,"abstract":"The demand for high-density, high-speed programming in flash memories has been increasing because their expanding applications in portable equipment such as digital still cameras and music players. A multilevel technique is one of the most effective approaches for improving memory density. But long cell programming time and precise control of the memory cell's threshold voltage (Vth) degrade its programming performance. To realize fast cell programming, we have developed a so-called assist-gate (AG)-AND-type flash cell, in which programming is performed by source side channel hot electron injection (SSI). In this paper, we developed a constant-charge-injection programming, which realizes fast precise control of Vth by suppressing the characteristic deviation. By utilizing proposed scheme, we achieved. 10.3-MB/s programming throughput in multilevel AG-AND flash memories.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124006573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An advanced fingerprint sensor LSI and its application to a fingerprint identification system 一种先进的指纹传感器LSI及其在指纹识别系统中的应用
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015103
H. Morimura, S. Shigematsu, T. Shimamura, K. Fujii, C. Yamaguchi, H. Suto, Y. Okazaki, K. Machida, H. Kyuragi
{"title":"An advanced fingerprint sensor LSI and its application to a fingerprint identification system","authors":"H. Morimura, S. Shigematsu, T. Shimamura, K. Fujii, C. Yamaguchi, H. Suto, Y. Okazaki, K. Machida, H. Kyuragi","doi":"10.1109/VLSIC.2002.1015103","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015103","url":null,"abstract":"We developed an advanced fingerprint sensor LSI that features a novel sensor structure, sensing circuit, and calibration circuit, using the 0.5-/spl mu/m CMOS process/sensor process. The LSI is reliable, sensitive, and tolerant to changes in the sensor surface conditions for capturing clear fingerprint image over long-term use. We also introduce a fingerprint-image adjustment scheme with an adjustable A/D converter to obtain image quality suitable for identification. The fingerprint sensor LSI was applied to a fingerprint identification system with the fingerprint-image adjustment scheme and achieved sufficient performance for a practical fingerprint identification system.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123522582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Designing a 3 GHz, 130 nm, Intel/sup /spl reg// Pentium/sup /spl reg// 4 processor 设计一个3ghz, 130nm, Intel/sup /spl reg// Pentium/sup /spl reg// 4处理器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015065
D. Deleganes, J. Douglas, B. Kommandur, M. Patyra
{"title":"Designing a 3 GHz, 130 nm, Intel/sup /spl reg// Pentium/sup /spl reg// 4 processor","authors":"D. Deleganes, J. Douglas, B. Kommandur, M. Patyra","doi":"10.1109/VLSIC.2002.1015065","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015065","url":null,"abstract":"The design of an IA32 processor fabricated in a state-of-the art 130 nm CMOS process with improved six layers of dual-damascene copper metallization is described. This paper describes the methodology employed to simultaneously achieve high frequency and low power in the Pentium/sup /spl reg// 4 processor, suitable for all segments-server, desktop, and mobile-meeting diverse challenges of performance, power delivery, and dissipation.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115956525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 400-MHz processor for the efficient conversion of rectangular to polar coordinates for digital communications applications 一个400-MHz处理器，用于数字通信应用的矩形到极坐标的有效转换
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015096
D.D. Hwang, Dengwei Fu, A. Willson
{"title":"A 400-MHz processor for the efficient conversion of rectangular to polar coordinates for digital communications applications","authors":"D.D. Hwang, Dengwei Fu, A. Willson","doi":"10.1109/VLSIC.2002.1015096","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015096","url":null,"abstract":"A 400-MHz digital rectangular-to-polar coordinate converter has been implemented in 0.25-/spl mu/m CMOS. The inputs to the chip are 14-bit in-phase and quadrature channels, and the outputs are 15-bit magnitude and phase channels. The phase and magnitude calculations have a maximum error of 0.00024 and 0.03, respectively. At a maximum frequency of 406 MHz, the circuit dissipates 470 mW of power at 2.5 V.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131991037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new architecture of programmable digital vision chip 一种新的可编程数字视觉芯片结构
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015100
T. Komuro, S. Kagami, M. Ishikawa
{"title":"A new architecture of programmable digital vision chip","authors":"T. Komuro, S. Kagami, M. Ishikawa","doi":"10.1109/VLSIC.2002.1015100","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015100","url":null,"abstract":"In this paper we propose a new architecture of digital vision chip, in which photo detectors and parallel processing elements designed in digital circuits are integrated together. In this architecture, the function to join several PEs is introduced and summation is calculated at high speed. Also, some sample algorithms and a 64/spl times/64 pixels prototype chip we developed will be described.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130068714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Analog front end IC for 3G WCDMA 模拟前端IC 3G WCDMA
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015034
Tsung-Yuan Chang, Xuewen Jiang, W. Khalil, S. R. Naqvi, B. Nikjou, J. Tseng
{"title":"Analog front end IC for 3G WCDMA","authors":"Tsung-Yuan Chang, Xuewen Jiang, W. Khalil, S. R. Naqvi, B. Nikjou, J. Tseng","doi":"10.1109/VLSIC.2002.1015034","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015034","url":null,"abstract":"Presents the world's first integrated analog front-end (AFE) and audio codec IC supporting the WCDMA standard. This chip was fabricated on Intel's 0.18 /spl mu/m flash+logic+analog (FLA) process technology using a 0.35 /spl mu/m feature size analog transistor. The AFE transmit path contains a 10-bit segmented R2R D/A, self-calibrated active RC filter and programmable gain amplifier (PGA) with a self tuning offset correction circuit. The receive path includes a programmable gain active RC filter and an 8-bit A/D with built-in offset correction. The AFE operates at 2.7 V with a current consumption of 55 mA, and total active area of 15 mm/sup 2/.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123587718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1.8 V digital A/D converter in 0.18 /spl mu/m CMOS 一个1.8 V数字A/D转换器在0.18 /spl mu/m CMOS
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015068
C. Braun, B. Engl
{"title":"A 1.8 V digital A/D converter in 0.18 /spl mu/m CMOS","authors":"C. Braun, B. Engl","doi":"10.1109/VLSIC.2002.1015068","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015068","url":null,"abstract":"A digital A/D converter (DAD) for audio applications is presented. The whole converter consists only of digital CMOS logic and some resistors and capacitors. No linear amplifier is needed. This kind of A/D converter is mostly a pure digital design. A prototype for 20 kHz audio applications with a 80 dB dynamic range and 44.1 kHz output sample rate was designed and processed in 0.18 /spl mu/m CMOS.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129427507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A general-purpose vector-quantization processor employing two-dimensional bit-propagating winner-take-all 一种采用二维比特传播赢者通吃的通用矢量量化处理器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015095
M. Ogawa, K. Ito, T. Shibata
{"title":"A general-purpose vector-quantization processor employing two-dimensional bit-propagating winner-take-all","authors":"M. Ogawa, K. Ito, T. Shibata","doi":"10.1109/VLSIC.2002.1015095","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015095","url":null,"abstract":"A general-purpose vector-quantization (VQ) processor featuring high-speed and versatile winner search functions is presented. A new two-dimensionally bit-propagating scheme has been employed in the winner-take-all (WTA) circuit. As a result, the maximum/minimum value identification for 6 b 128 inputs in a single clock cycle has been accomplished, which is five times faster than the conventional approach (18 b comparison is carried out in three clock cycles). In addition, the new block addressing scheme developed in the present work enables various options in WTA operations. The chip was fabricated in a standard CMOS process and the operation was demonstrated by application to handwritten character recognition as an example.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130551551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Design and validation of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors power delivery 设计和验证Pentium/sup /spl reg// III和Pentium/sup /spl reg// 4处理器的功率传输
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015090
T. Rahal-Arabi, G. Taylor, M. Ma, C. Webb
{"title":"Design and validation of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors power delivery","authors":"T. Rahal-Arabi, G. Taylor, M. Ma, C. Webb","doi":"10.1109/VLSIC.2002.1015090","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015090","url":null,"abstract":"In this paper, we present an empirical approach for the validation of the power supply impedance model. The model is widely used to design the power delivery for high performance systems. For this purpose, several silicon wafers of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors were built with various amount of decoupling. The measured data showed significant discrepancies with the model predictions and provided useful insights in investigating the model regions of validity.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133288380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
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