Design and validation of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors power delivery

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015090

T. Rahal-Arabi, G. Taylor, M. Ma, C. Webb

引用次数: 41

Abstract

In this paper, we present an empirical approach for the validation of the power supply impedance model. The model is widely used to design the power delivery for high performance systems. For this purpose, several silicon wafers of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors were built with various amount of decoupling. The measured data showed significant discrepancies with the model predictions and provided useful insights in investigating the model regions of validity.

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设计和验证Pentium/sup /spl reg// III和Pentium/sup /spl reg// 4处理器的功率传输

在本文中，我们提出了一种验证电源阻抗模型的经验方法。该模型被广泛应用于高性能系统的电力输送设计。为此，Pentium/sup /spl reg// III和Pentium/sup /spl reg// 4处理器的几个硅晶片被构建成不同数量的去耦。实测数据显示了与模型预测的显著差异，并为研究模型的有效性区域提供了有用的见解。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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