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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)最新文献

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A 5 Gbps CMOS frequency tolerant multi phase clock recovery circuit 5 Gbps CMOS容频多相时钟恢复电路
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015052
Toru Iwata, Takashi Hirata, Hirokazu Sugimoto, Hideki Kimura, T. Yoshikawa
{"title":"A 5 Gbps CMOS frequency tolerant multi phase clock recovery circuit","authors":"Toru Iwata, Takashi Hirata, Hirokazu Sugimoto, Hideki Kimura, T. Yoshikawa","doi":"10.1109/VLSIC.2002.1015052","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015052","url":null,"abstract":"A clock and data recovery (CDR) circuit using multi phase gated VCO (MGVCO) technique for multi-channel high-speed serial interface was developed. This architecture can realize quick data acquisition and plesiochronous clocking capability. A 5 Gbps 32-channel test chip, designed in 0.18 /spl mu/m CMOS technology, achieved BER of <10/sup -12/ in 5 Gbps CDR operation with /spl plusmn/3% frequency tolerance for random incoming data of 2/sup 7/-1.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132784954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Near speed-of-light on-chip electrical interconnect 接近光速的芯片上电气互连
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015032
R. Chang
{"title":"Near speed-of-light on-chip electrical interconnect","authors":"R. Chang","doi":"10.1109/VLSIC.2002.1015032","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015032","url":null,"abstract":"The propagation limits of electrical signals for systems built with conventional silicon processing are explored. Data transmission near the speed of light with an all-electrical system can be achieved by taking advantage of the inductance-dominated high-frequency regime of on-chip interconnect. In a 0.18 /spl mu/m, 6-level Aluminum CMOS technology, an overall delay of 278 ps for a 20 mm long line corresponding to a propagation velocity of one half the speed of light in silicon dioxide has been demonstrated.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115420254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 2.9ns random access cycle embedded DRAM with a destructive-read 一个2.9ns随机存取周期嵌入DRAM与破坏性读取
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015077
C.L. Hwang, T. Kirihata, M. Wordernan, J. Fifield, D. Storaska, D. Pontius, G. Fredernan, B. Ji, S. Tomashot, S. Dhong
{"title":"A 2.9ns random access cycle embedded DRAM with a destructive-read","authors":"C.L. Hwang, T. Kirihata, M. Wordernan, J. Fifield, D. Storaska, D. Pontius, G. Fredernan, B. Ji, S. Tomashot, S. Dhong","doi":"10.1109/VLSIC.2002.1015077","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015077","url":null,"abstract":"High performance devices available in a logic-based embedded DRAM process can be used to significantly improve eDRAM performance. However, random access cycle time of conventional eDRAMs remains around 6 ns. In this work, a novel destructive-read architecture that reduces the random access cycle time of an eDRAM by delaying the data write back operation to a later cycle is demonstrated. A single-ended direct sensing is employed to further speed up the random access cycle time of the eDRAM to 2.9ns.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130386451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Dual supply voltage clocking for 5 GHz 130 nm integer execution core 双电源电压时钟的5 GHz 130纳米整数执行核心
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015121
Ram K. Krishnamurthy, S. Hsu, M. Anders, B. Bloechel, B. Chatterjee, M. Sachdev, S. Borkar
{"title":"Dual supply voltage clocking for 5 GHz 130 nm integer execution core","authors":"Ram K. Krishnamurthy, S. Hsu, M. Anders, B. Bloechel, B. Chatterjee, M. Sachdev, S. Borkar","doi":"10.1109/VLSIC.2002.1015121","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015121","url":null,"abstract":"This paper describes dual-V/sub cc/ clocking on a 1.2 V, 5 GHz integer execution core fabricated in 130 nm CMOS to achieve up to 71% measured clock power (including 15% active leakage) reduction. A write-port style pass-transistor latch and split-output level-converting local clock buffer are described for robust, DC power free low-V/sub cc/ clock operation.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128723952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing 使用双v /sub /分配和晶体管尺寸组合的高性能微处理器的设计优化
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015089
J. Tschanz, Y. Ye, Liqiong Wei, V. Govindarajulu, N. Borkar, S. Burns, T. Karnik, S. Borkar, V. De
{"title":"Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing","authors":"J. Tschanz, Y. Ye, Liqiong Wei, V. Govindarajulu, N. Borkar, S. Burns, T. Karnik, S. Borkar, V. De","doi":"10.1109/VLSIC.2002.1015089","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015089","url":null,"abstract":"Joint optimizations of dual-V/sub T/ allocation and transistor sizing reduce low-V/sub T/ usage by 36%-45% and leakage power by 20% in a high performance microprocessor, with minimal impact on total active power and die area. An enhancement of the optimum design allows processor frequency to be increased efficiently during manufacturing.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"152 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114003692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
A 6.5 GHz CMOS FSK modulator for wireless sensor applications 用于无线传感器应用的6.5 GHz CMOS FSK调制器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-01 DOI: 10.1109/VLSIC.2002.1015079
Seonghwan Cho, A. Chandrakasan
{"title":"A 6.5 GHz CMOS FSK modulator for wireless sensor applications","authors":"Seonghwan Cho, A. Chandrakasan","doi":"10.1109/VLSIC.2002.1015079","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015079","url":null,"abstract":"A 6.5 GHz FSK modulator suitable for low power wireless sensor network is presented. The modulator employs closed loop direct VCO modulation to achieve high data rate, variable loop bandwidth technique for fast start-up rates and /spl Sigma/-/spl Delta/ for reduced power consumption in the divider with fine resolution in channel selection. The synthesizer, implemented in 0.25 /spl mu/m CMOS, achieves 20 /spl mu/s start-up time with an effective data rate of 2.5 Mbps while consuming 22 mW.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121404897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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