使用双v /sub /分配和晶体管尺寸组合的高性能微处理器的设计优化

J. Tschanz, Y. Ye, Liqiong Wei, V. Govindarajulu, N. Borkar, S. Burns, T. Karnik, S. Borkar, V. De
{"title":"使用双v /sub /分配和晶体管尺寸组合的高性能微处理器的设计优化","authors":"J. Tschanz, Y. Ye, Liqiong Wei, V. Govindarajulu, N. Borkar, S. Burns, T. Karnik, S. Borkar, V. De","doi":"10.1109/VLSIC.2002.1015089","DOIUrl":null,"url":null,"abstract":"Joint optimizations of dual-V/sub T/ allocation and transistor sizing reduce low-V/sub T/ usage by 36%-45% and leakage power by 20% in a high performance microprocessor, with minimal impact on total active power and die area. An enhancement of the optimum design allows processor frequency to be increased efficiently during manufacturing.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"152 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"50","resultStr":"{\"title\":\"Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing\",\"authors\":\"J. Tschanz, Y. Ye, Liqiong Wei, V. Govindarajulu, N. Borkar, S. Burns, T. Karnik, S. Borkar, V. De\",\"doi\":\"10.1109/VLSIC.2002.1015089\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Joint optimizations of dual-V/sub T/ allocation and transistor sizing reduce low-V/sub T/ usage by 36%-45% and leakage power by 20% in a high performance microprocessor, with minimal impact on total active power and die area. An enhancement of the optimum design allows processor frequency to be increased efficiently during manufacturing.\",\"PeriodicalId\":162493,\"journal\":{\"name\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"volume\":\"152 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"50\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2002.1015089\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2002.1015089","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 50

摘要

双v /sub - T/分配和晶体管尺寸的联合优化使高性能微处理器的低v /sub - T/使用率降低了36%-45%,泄漏功率降低了20%,而对总有功功率和芯片面积的影响最小。优化设计的增强允许处理器频率在制造过程中有效地增加。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing
Joint optimizations of dual-V/sub T/ allocation and transistor sizing reduce low-V/sub T/ usage by 36%-45% and leakage power by 20% in a high performance microprocessor, with minimal impact on total active power and die area. An enhancement of the optimum design allows processor frequency to be increased efficiently during manufacturing.
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