Dual supply voltage clocking for 5 GHz 130 nm integer execution core

Abstract

This paper describes dual-V/sub cc/ clocking on a 1.2 V, 5 GHz integer execution core fabricated in 130 nm CMOS to achieve up to 71% measured clock power (including 15% active leakage) reduction. A write-port style pass-transistor latch and split-output level-converting local clock buffer are described for robust, DC power free low-V/sub cc/ clock operation.