5 Gbps CMOS容频多相时钟恢复电路

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015052

Toru Iwata, Takashi Hirata, Hirokazu Sugimoto, Hideki Kimura, T. Yoshikawa

{"title":"5 Gbps CMOS容频多相时钟恢复电路","authors":"Toru Iwata, Takashi Hirata, Hirokazu Sugimoto, Hideki Kimura, T. Yoshikawa","doi":"10.1109/VLSIC.2002.1015052","DOIUrl":null,"url":null,"abstract":"A clock and data recovery (CDR) circuit using multi phase gated VCO (MGVCO) technique for multi-channel high-speed serial interface was developed. This architecture can realize quick data acquisition and plesiochronous clocking capability. A 5 Gbps 32-channel test chip, designed in 0.18 /spl mu/m CMOS technology, achieved BER of <10/sup -12/ in 5 Gbps CDR operation with /spl plusmn/3% frequency tolerance for random incoming data of 2/sup 7/-1.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 5 Gbps CMOS frequency tolerant multi phase clock recovery circuit\",\"authors\":\"Toru Iwata, Takashi Hirata, Hirokazu Sugimoto, Hideki Kimura, T. Yoshikawa\",\"doi\":\"10.1109/VLSIC.2002.1015052\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A clock and data recovery (CDR) circuit using multi phase gated VCO (MGVCO) technique for multi-channel high-speed serial interface was developed. This architecture can realize quick data acquisition and plesiochronous clocking capability. A 5 Gbps 32-channel test chip, designed in 0.18 /spl mu/m CMOS technology, achieved BER of <10/sup -12/ in 5 Gbps CDR operation with /spl plusmn/3% frequency tolerance for random incoming data of 2/sup 7/-1.\",\"PeriodicalId\":162493,\"journal\":{\"name\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2002.1015052\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2002.1015052","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

设计了一种基于多相门控VCO (MGVCO)技术的多通道高速串行接口时钟与数据恢复(CDR)电路。该体系结构可以实现快速的数据采集和准同步的时钟功能。采用0.18 /spl mu/m CMOS技术设计的5gbps 32通道测试芯片，在5gbps CDR操作中实现了<10/sup -12/的误码率，对随机输入数据的/spl plusmn/3%的频率容差为2/sup 7/-1。

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A 5 Gbps CMOS frequency tolerant multi phase clock recovery circuit

A clock and data recovery (CDR) circuit using multi phase gated VCO (MGVCO) technique for multi-channel high-speed serial interface was developed. This architecture can realize quick data acquisition and plesiochronous clocking capability. A 5 Gbps 32-channel test chip, designed in 0.18 /spl mu/m CMOS technology, achieved BER of <10/sup -12/ in 5 Gbps CDR operation with /spl plusmn/3% frequency tolerance for random incoming data of 2/sup 7/-1.

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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