S. Ramaswamy, V. Gupta, P. Landman, B. Parthasarathy, R. Gu, A. Yee, L. Dyson, S. Wu, W. Lee
{"title":"Programmable termination for CML I/O's in high speed CMOS transceivers","authors":"S. Ramaswamy, V. Gupta, P. Landman, B. Parthasarathy, R. Gu, A. Yee, L. Dyson, S. Wu, W. Lee","doi":"10.1109/VLSIC.2002.1015049","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015049","url":null,"abstract":"This paper describes I/O circuits that can be used in high-speed transceivers to communicate with next generation and legacy devices. We describe the transmitter and receiver front-end circuits that are designed to operate with dual termination voltage supplies. The receiver characterization, ESD protection and system level power up issues related to gate-oxide and electro-migration reliability are discussed.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131858038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Wuensche, M. Jacunski, H. Streif, A. Sturm, J. Morrish, M. Roberge, M. Clark, T. Nostrand, E. Stahl, S. Lewis, J. Heath, M. Wood, T. Vogelsang, E. Thoma, J. Gabric, M. Kleiner, M. Killian, P. Poechmueller, W. Mueller, G. Bronner
{"title":"A 110 nm 512 Mb DDR DRAM with vertical transistor trench cell","authors":"S. Wuensche, M. Jacunski, H. Streif, A. Sturm, J. Morrish, M. Roberge, M. Clark, T. Nostrand, E. Stahl, S. Lewis, J. Heath, M. Wood, T. Vogelsang, E. Thoma, J. Gabric, M. Kleiner, M. Killian, P. Poechmueller, W. Mueller, G. Bronner","doi":"10.1109/VLSIC.2002.1015059","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015059","url":null,"abstract":"This paper describes a 512 Mb DDR SDRAM in 110 nm technology based on a highly cost efficient 8F/sup 2/ trench capacitor cell with a double gate vertical pass transistor. The product also features a bitline voltage generator using a distributed output transistor with a power supply IR-drop correction scheme. A read/write selective column activation circuit is employed to optimize high frequency operation.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130496487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Boeun Kim, Seyeob Kim, Tae-Ju Lee, Jin-Kyu Lim, Young-jin Kim, M. Jeong, K. Kim, Sung-Uk Kim, Sung-Ho Park, B. Ko
{"title":"A CMOS single-chip direct conversion satellite receiver for digital broadcasting system","authors":"Boeun Kim, Seyeob Kim, Tae-Ju Lee, Jin-Kyu Lim, Young-jin Kim, M. Jeong, K. Kim, Sung-Uk Kim, Sung-Ho Park, B. Ko","doi":"10.1109/VLSIC.2002.1015094","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015094","url":null,"abstract":"This paper presents a fully integrated single-chip direct conversion receiver for DBS system. The receiver tunes 950-2150 MHz wide band using integrated low phase noise VCOs and a fractional-N phase locked loop. Fully programmable 2-58 MHz cut-off frequency channel select filter effectively eliminates out-of-channel jammers to increase the linearity and optimize its performance for the 1-45 Msps variable data rates. A delta-sigma modulated fractional-N synthesizer with low noise quadrature VCOs exhibits phase noise of -76 dBc/Hz at 10 kHz offset. It has a -65 dBm sensitivity with an 80 dB system gain dynamic range. The receiver draws only 100 mA from 1.8 V supply. This low power highly integrated DBS receiver uses a 0.18 /spl mu/m CMOS process.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124223380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Franca-Neto, P. Pardy, M. P. Ly, R. Rangel, S. Suthar, T. Syed, B. Bloechel, S. Lee, C. Burnett, D. Cho, D. Kau, A. Fazio, K. Soumyanath
{"title":"Enabling high-performance mixed-signal system-on-a-chip (SoC) in high performance logic CMOS technology","authors":"L. Franca-Neto, P. Pardy, M. P. Ly, R. Rangel, S. Suthar, T. Syed, B. Bloechel, S. Lee, C. Burnett, D. Cho, D. Kau, A. Fazio, K. Soumyanath","doi":"10.1109/VLSIC.2002.1015074","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015074","url":null,"abstract":"Presents a technique to enable the integration of sensitive analog circuits with a Pentium class microprocessor, on a lossy substrate that sees 190 mVrms of equivalent noise at the center of the die. Measurement results of substrate noise on a Pentium 4/spl reg/ 1 GHz processor show that we can exploit the spectral content of this noise, and use appropriately tuned analog amplification to limit the isolation requirements to 70 dB. By using a combination of measurement and field solver results, we show that a minimal process enhancement (i.e. a deep nwell) will yield 50 dB of isolation. We use measured mismatch data and analysis to conclude that the remaining 20 dB can be achieved by symmetric matched layouts and fully differential circuit topologies. We describe two deep nwell biasing techniques (substrate noise trapping and floating deep nwell) to realize the 50 dB on-die isolation. Finally, we use measurements to show that the deep nwell does not adversely impact the high frequency performance of 140 nm logic CMOS devices.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125127335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Technology trends of high-definition digital still camera systems","authors":"H. Tamayama, K. Ito, T. Nishimura","doi":"10.1109/VLSIC.2002.1015056","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015056","url":null,"abstract":"In the recent several years, the digital still camera (DSC) has achieved a remarkable progress in terms of pixel numbers, compactness, performance, and power consumption, mainly owing to the progress in silicon technology. This report summarizes the technological trends of DSC, with particular attention given to CCD image sensors, digital/analog LSI, and recording media, and incorporation in DSC.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131392281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Hyde, T. Humes, C. Diorio, M. Thomas, M. Figueroa
{"title":"A floating-gate trimmed, 14-bit, 250 Ms/s digital-to-analog converter in standard 0.25 /spl mu/m CMOS","authors":"J. Hyde, T. Humes, C. Diorio, M. Thomas, M. Figueroa","doi":"10.1109/VLSIC.2002.1015118","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015118","url":null,"abstract":"We describe a floating-gate trimmed, 14-bit, 250 Ms/s current-steered DAC fabricated in a 0.25 /spl mu/m CMOS logic process. We trim the static INL to /spl plusmn/0.3 LSB using analog charge stored on floating-gate pFETs. The DAC occupies 0.44 mm/sup 2/ of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves 72 dB SFDR at 250 Ms/s.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131426109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes","authors":"B. Casper, Matthew Haycock, R. Mooney","doi":"10.1109/VLSIC.2002.1015043","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015043","url":null,"abstract":"This paper introduces an accurate method of modeling the performance of high-speed chip-to-chip signaling systems. Implemented in a simulation tool, it precisely accounts for intersymbol interference, cross-talk and echos as well as circuit related effects such as thermal noise, power supply noise and receiver jitter. We correlated the simulation tool to actual measurements of a high-speed signaling system and then used this tool to make tradeoffs between different methods of chip-to-chip signaling with and without equalization.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131524556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 1.2 Gbps CMOS DFE receiver with the extended sampling time window for application to the SSTL channel","authors":"Y. Sohn, Seungsoo Bae, Hong-June Park, Sooin Cho","doi":"10.1109/VLSIC.2002.1015055","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015055","url":null,"abstract":"A CMOS DFE (decision feedback equalization) receiver with a negligible overhead in chip area and power consumption was implemented by cross-coupling the outputs of a conventional 2-way interleaving receiver to the other side of the input. Application of this receiver to the SSTL interface channel showed the increase of sampling time window by 60 /spl sim/120% at data rates from 800 Mbps up to 1.2 Gbps. Chip area and power consumption are 80/spl times/100 /spl mu/m and 2.5 mW respectively with a 0.25 /spl mu/m 1-poly 5-metal CMOS process at the supply voltage of 2.5 V.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126496694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-/spl mu/m CMOS process","authors":"J. Wong, V. Cheung, H. Luong","doi":"10.1109/VLSIC.2002.1015081","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015081","url":null,"abstract":"A 1-V high-speed dynamic frequency divider using a common-gate topology is proposed. A simple and accurate small-signal analysis model is provided to estimate the operating frequencies. Implemented in a standard 0.35-/spl mu/m digital CMOS process and at 1-V supply, the proposed frequency divider measures an operating frequency up to 5.2 GHz at a power consumption of 2.5 mW.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132096703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A low power 200 MHz receiver for wireless hearing aid devices","authors":"A. Deiss, Qiuting Huang","doi":"10.3929/ETHZ-A-004319590","DOIUrl":"https://doi.org/10.3929/ETHZ-A-004319590","url":null,"abstract":"A low power receiver for a wireless hearing aid system working in the 174-223 MHz range has been implemented in a 0.8 /spl mu/m BiCMOS technology. The chip comprises LNA, RF-mixer, variable-gain IF-amplifier, and demodulator, which consists of digital phase-shifter and I/Q IF-mixers, 5th order Bessel filters, and DC-amplifiers. Merely 667 /spl mu/A including biasing is consumed for the reception of an 8-ary PSK signal with 336 kbit/s.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133844834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}