A 110 nm 512 Mb DDR DRAM with vertical transistor trench cell

Abstract

This paper describes a 512 Mb DDR SDRAM in 110 nm technology based on a highly cost efficient 8F/sup 2/ trench capacitor cell with a double gate vertical pass transistor. The product also features a bitline voltage generator using a distributed output transistor with a power supply IR-drop correction scheme. A read/write selective column activation circuit is employed to optimize high frequency operation.