1 v 2.5 mw 5.2 ghz分频器，0.35-/spl mu/m CMOS工艺

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015081

J. Wong, V. Cheung, H. Luong

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引用次数: 19

摘要

提出了一种采用共门拓扑结构的1v高速动态分频器。给出了一种简单、准确的小信号分析模型来估计工作频率。在标准的0.35-/spl mu/m数字CMOS工艺和1v电源下实现，所提出的分频器在功耗为2.5 mW的情况下测量工作频率高达5.2 GHz。

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A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-/spl mu/m CMOS process

A 1-V high-speed dynamic frequency divider using a common-gate topology is proposed. A simple and accurate small-signal analysis model is provided to estimate the operating frequencies. Implemented in a standard 0.35-/spl mu/m digital CMOS process and at 1-V supply, the proposed frequency divider measures an operating frequency up to 5.2 GHz at a power consumption of 2.5 mW.

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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