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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)最新文献

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Four-way processor 800 MT/s front side bus with ground referenced voltage source I/O 四路处理器800 MT/s前端总线与接地参考电压源I/O
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015048
T. Thomas, I. Young
{"title":"Four-way processor 800 MT/s front side bus with ground referenced voltage source I/O","authors":"T. Thomas, I. Young","doi":"10.1109/VLSIC.2002.1015048","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015048","url":null,"abstract":"A 40 cm multi-drop bus shared by 5 test chips to emulate 4 processors and a chipset runs error free at 800 MT/s with 130 mV margin using Ground Referenced Voltage Source (GRVS) I/O scheme. For comparison, when the same test chip is programmed to use Gunning Transceiver Logic (GTL), the bus speed is 500 MT/s for the same 130 mV margin under identical conditions.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114428424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Ultralow-power CMOS/SOI LSI design for future mobile systems 未来移动系统的超低功耗CMOS/SOI LSI设计
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015028
T. Douseki, J. Yamada, H. Kyuragi
{"title":"Ultralow-power CMOS/SOI LSI design for future mobile systems","authors":"T. Douseki, J. Yamada, H. Kyuragi","doi":"10.1109/VLSIC.2002.1015028","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015028","url":null,"abstract":"Ultralow-power CMOS/SOI circuit technology that uses fully-depleted SOI and multi-threshold (MT) CMOS circuits makes it possible to lower the supply voltage to 0.5 V and reduce the power dissipation of LSIs to 1 /spl sim/ 10 mW without any speed loss. We overview the ultralow-power CMOS/SOI circuit technology and some ultralow-voltage LSIs based on MTCMOS/SOI circuits.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131617614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A still image encoder based on adaptive resolution vector quantization realizing compression ratio over 1/200 featuring needless calculation elimination architecture 一种基于自适应分辨率矢量量化的静态图像编码器，压缩比超过1/200，具有不必要的计算消除结构
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015099
M. Fujibayashi, T. Nozawa, T. Nakayama, K. Mochizuki, M. Konda, K. Kotani, S. Sugawa, T. Ohmi
{"title":"A still image encoder based on adaptive resolution vector quantization realizing compression ratio over 1/200 featuring needless calculation elimination architecture","authors":"M. Fujibayashi, T. Nozawa, T. Nakayama, K. Mochizuki, M. Konda, K. Kotani, S. Sugawa, T. Ohmi","doi":"10.1109/VLSIC.2002.1015099","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015099","url":null,"abstract":"We have developed an advanced vector quantization (VQ) encoding hardware for still image encoding systems. By utilizing needless calculation elimination method, computational cost of VQ encoding is reduced to 40% or less, while maintaining the accuracy of full-search VQ. We have also developed a still image compression algorithm based on adaptive resolution VQ (AR-VQ), which realizes compression ratio over 1/200 while maintaining image quality. We have successfully implemented these two technologies into a still image encoding processor. The processor can compress still image of 1600/spl times/2400 pixels within one second, which is 60 times faster than software implementation on current PCs.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134318953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multi-mode CMOS low dropout voltage regulator for GSM handsets 用于GSM手机的多模CMOS低差稳压器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015106
T. Barber, S. Ho, P. Ferguson
{"title":"Multi-mode CMOS low dropout voltage regulator for GSM handsets","authors":"T. Barber, S. Ho, P. Ferguson","doi":"10.1109/VLSIC.2002.1015106","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015106","url":null,"abstract":"This paper presents a 1.8 V 400 mA multi-mode low dropout voltage regulator designed in a 0.25 /spl mu/m CMOS process. Multiple power modes are used to increase the efficiency of the regulator under both heavy and light loads. Under heavy loads, a high power driver with dynamic current bias and a DC/DC converter are used to improve the efficiency from 50% to 75%. Under light loads, a low power driver is used to improve the efficiency from 0.2% to 43.5%.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132079073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current mram写入电路补偿磁化反转电流的热变化
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015072
T. Honda, N. Sakimura, T. Sugibayashi, S. Miura, H. Numata, H. Hada, S. Tahara
{"title":"MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current","authors":"T. Honda, N. Sakimura, T. Sugibayashi, S. Miura, H. Numata, H. Hada, S. Tahara","doi":"10.1109/VLSIC.2002.1015072","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015072","url":null,"abstract":"MRAM-writing circuitry to compensate for the thermal variation of the magnetization-reversal current (MRC) is proposed. The writing current of the proposed circuitry is designed to decrease in proportion to an increase in temperature. This technique prevents multiple-write (MW) failures from degrading 1Gb MRAM yield where the standard deviation of MRC variation from other origins is less than 5%.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121082394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
/spl mu/I/O architecture for 0.13-/spl mu/m wide-voltage-range system-on-a-package (SoP) designs /spl mu/I/O架构适用于0.13-/spl mu/m宽电压范围的单包系统(SoP)设计
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015075
Y. Kanno, H. Mizuno, N. Oodaira, Y. Yasu, K. Yanagisawa
{"title":"/spl mu/I/O architecture for 0.13-/spl mu/m wide-voltage-range system-on-a-package (SoP) designs","authors":"Y. Kanno, H. Mizuno, N. Oodaira, Y. Yasu, K. Yanagisawa","doi":"10.1109/VLSIC.2002.1015075","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015075","url":null,"abstract":"To provide low-cost system solutions together with a 0.13-/spl mu/m dual-t/sub ox/ CMOS and multi-chip package (MCP) technologies, a new, so-called /spl mu/I/O architecture was developed. The /spl mu/I/O provides a common interface throughout the module and, thus, enables high design reusability and hierarchical I/O design for MCPs. The /spl mu/I/O includes a signal-level converter for integrating wide-voltage-range (0.75-1.3 or 1.5-3.6 V) circuit blocks, and a signal wall function for turning off each block independently - without invalid signal transmission - by using an internal power switch.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126883994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A low-noise 2-GB/s 256-Mb packet-based DRAM with a robust array power supply 低噪声2gb /s 256 mb基于分组的DRAM，具有强大的阵列电源
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015060
K. Kwon, B. Moon, Changhyun Kim, Sooin Cho
{"title":"A low-noise 2-GB/s 256-Mb packet-based DRAM with a robust array power supply","authors":"K. Kwon, B. Moon, Changhyun Kim, Sooin Cho","doi":"10.1109/VLSIC.2002.1015060","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015060","url":null,"abstract":"With a robust array power supply, the array noise is remarkably suppressed in 256-Mb packet-based DRAM. The array power supply is equipped with direct driver discharge, Vgs clamp, high-VCC compensator, and low-VCC Vgs booster. The VCCA drop and overshoot are improved from 133 mV to 70 mV and from 260 mV to 120 mV, respectively, as all these features are included. The tranquil VCCA results in active restoration improvement by 3.0 ns in the full chip performance. The suppression of the VCCA overshoot makes high speed operation reliable owing to rapid column precharge. The power consumption by the VCCA generator is also reduced by 35% because of the time-variant DC current control.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128690980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.6 Gb/s, 3 mW CMOS receiver for optical communication 用于光通信的1.6 Gb/s, 3mw CMOS接收器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015053
A. Emami-Neyestanak, D. Liu, G. Keeler, N. Helman, M. Horowitz
{"title":"A 1.6 Gb/s, 3 mW CMOS receiver for optical communication","authors":"A. Emami-Neyestanak, D. Liu, G. Keeler, N. Helman, M. Horowitz","doi":"10.1109/VLSIC.2002.1015053","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015053","url":null,"abstract":"A 1.6 Gb/s receiver for optical communication has been designed and fabricated in a 0.25-/spl mu/m CMOS process. This receiver has no transimpedance amplifier and uses the parasitic capacitor of the flip-chip bonded photodetector as an integrating element and resolves the data with a double-sampling technique. A simple feedback loop adjusts a bias current to the average optical signal, which essentially \"AC couples\" the input. The resulting receiver resolves an 11 /spl mu/A input, dissipates 3 mW of power, occupies 80 /spl mu/m/spl times/50 /spl mu/m of area and operates at over 1.6 Gb/s.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130594054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Leakage-biased domino circuits for dynamic fine-grain leakage reduction 用于动态细颗粒泄漏减少的泄漏偏置多米诺电路
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015114
Seongmoo Heo, K. Asanović
{"title":"Leakage-biased domino circuits for dynamic fine-grain leakage reduction","authors":"Seongmoo Heo, K. Asanović","doi":"10.1109/VLSIC.2002.1015114","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015114","url":null,"abstract":"A leakage-biased domino circuit family is proposed that maintains high speed in active mode but which can be rapidly placed into a low-leakage inactive state by using leakage currents themselves to bias internal nodes. A 32-bit Han-Carlson domino adder circuit is used to compare LB-domino with conventional single and dual Vt domino circuits. For equal delay and noise margin, the LB-domino technique gives two decades reduction in steady-state leakage energy compared to a dual-Vt technique.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129922908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
A 0.13-/spl mu/m CMOS 5-Gb/s 10-meter 28 AWG cable transceiver with no-feedback-loop continuous-time post-equalizer 一个0.13-/spl mu/m CMOS 5gb /s 10米28 AWG电缆收发器，无反馈回路连续时间后均衡器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015046
Y. Kudoh, M. Fukaishi, M. Mizuno
{"title":"A 0.13-/spl mu/m CMOS 5-Gb/s 10-meter 28 AWG cable transceiver with no-feedback-loop continuous-time post-equalizer","authors":"Y. Kudoh, M. Fukaishi, M. Mizuno","doi":"10.1109/VLSIC.2002.1015046","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015046","url":null,"abstract":"A 5-Gb/s 10-meter 28 AWG cable transceiver is developed with 0.13-/spl mu/m CMOS technologies. A continuous-time post-equalizer with the novel high-speed analog amplifiers can handle up to 9 dB of frequency-dependent attenuation in cables, and an 18 dB of improvement in the attenuation (27 dB in total) can be also achieved with the novel optimization technique using the pre-emphasis and the post-equalization.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121542972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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