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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)最新文献

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Fully-parallel pattern-matching engine with dynamic adaptability to Hamming or Manhattan distance 全平行模式匹配引擎与动态适应汉明或曼哈顿距离
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015097
H. Mattausch, N. Omori, S. Fukae, T. Koide, T. Gyoten
{"title":"Fully-parallel pattern-matching engine with dynamic adaptability to Hamming or Manhattan distance","authors":"H. Mattausch, N. Omori, S. Fukae, T. Koide, T. Gyoten","doi":"10.1109/VLSIC.2002.1015097","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015097","url":null,"abstract":"The proposed pattern-matching engine achieves distance-measure adaptability through pattern encoding and can therefore cover a wide range of high-performance real-time applications. Key to short nearest-match times is a compact fully-parallel associative-memory core. The performance of a 9.75 mm/sup 2/ test-circuit in 0.6 /spl mu/m CMOS technology is about equivalent to a 32 bit computer with ITOPS. The test-circuit suggests possible pattern length /spl ges/768 equivalent bit, >10/sup 7/ pattern/sec throughput, <1.13% winner-input-distance error and <1.35 mW power dissipation per reference pattern.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123243634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 1.2 V 10-b 100-MSamples/s A/D converter in 0.12/spl mu/m CMOS 一个1.2 V 10-b 100-MSamples/s A/D转换器在0.12/spl mu/m CMOS
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015117
A. Blum, B. Engl, H. Eichfeld, R. Hagelauer, A. Abidi
{"title":"A 1.2 V 10-b 100-MSamples/s A/D converter in 0.12/spl mu/m CMOS","authors":"A. Blum, B. Engl, H. Eichfeld, R. Hagelauer, A. Abidi","doi":"10.1109/VLSIC.2002.1015117","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015117","url":null,"abstract":"A CMOS analog-to-digital converter (ADC) utilizing folding, averaging and distributed interpolation is described. Fabricated in a digital 0.12 /spl mu/m CMOS process, the ADC occupies 0.32 mm/sup 2/ while dissipating 140 mW from a single 1.2 V supply. The experimental results show that the converter achieves 55dB SNR at sampling frequencies up to 100MHz.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130048719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 40 GHz VCO with 9 to 15% tuning range in 0.13 /spl mu/m SOI CMOS 在0.13 /spl mu/m SOI CMOS中具有9至15%调谐范围的40 GHz压控振荡器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015080
N. Fong, J. Plouchart, N. Zamdmer, Duixian Liu, L. Wagner, P. Garry, G. Tarr
{"title":"A 40 GHz VCO with 9 to 15% tuning range in 0.13 /spl mu/m SOI CMOS","authors":"N. Fong, J. Plouchart, N. Zamdmer, Duixian Liu, L. Wagner, P. Garry, G. Tarr","doi":"10.1109/VLSIC.2002.1015080","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015080","url":null,"abstract":"A 40 GHz fully-monolithic complementary VCO fabricated in IBM 0.13 /spl mu/m partially-depleted SOI CMOS technology is reported. The VCO operates at 1.5 V supply and draws 11.25 mW of power. The measured phase noise at 40 GHz is -109 dBc/Hz at 4 MHz offset from the carrier. At 1.5 V and 2 V V/sub DD/, the tuning range is 9% and 15% respectively, and the output power is -8 dBm and -5 dBm respectively. The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126120031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Crosstalk delay analysis of a 0.13-/spl mu/m-node test chip and precise gate-level simulation technology 一个0.13-/spl μ /m节点的串扰延迟分析测试芯片和精确门级仿真技术
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015086
Y. Sasaki, M. Satoh, M. Kuramoto, F. Kikuchi, T. Kawashima, H. Masuda, K. Yano
{"title":"Crosstalk delay analysis of a 0.13-/spl mu/m-node test chip and precise gate-level simulation technology","authors":"Y. Sasaki, M. Satoh, M. Kuramoto, F. Kikuchi, T. Kawashima, H. Masuda, K. Yano","doi":"10.1109/VLSIC.2002.1015086","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015086","url":null,"abstract":"The impact of crosstalk on the delay was examined by measuring a test chip manufactured with a 0.13-/spl mu/m-node technology. This examination revealed three requirements for precise and fast gate-level simulation technology: (1) consideration of degradation change dependent on relative-signal-arrival-time over a wide range, (2) static timing analysis (STA) based operation, and (3) quantitative estimation of the degradation accumulation caused by multiple aggressors. A candidate for such simulation technology is provided. and its highly precise characteristic is demonstrated through measurements and simulations. In a test structure with a two-aggressor crosstalk, the maximum error between the measured and simulated degradations was reduced to less than one sixth of that with a conventional method.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126563374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 125MHz burst mode 0.18/spl mu/m 128Mbit 2 bits per cell flash memory 一种125MHz突发模式0.18/spl mu/m 128Mbit / cell 2位闪存
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015111
H. Castro, K. Augustine, S. Balasubrahmanyam, T. Bressie, S. Chandramouli, G. Christensen, M. Dayley, D. Elmhurst, K. Fan, M. Goldman, C. Haid, R. Haque, M. Ishac, M. Khandaker, J. Kreifels, B. Li, K. Loe, T. Ly, F. Marvin, R. Melcher, S. Monasa, R. Nambiar, Q. Ngo, R. Padilla, B. Pathak, A. Rahman, R. Rajagopal, K. Ramamurthi, S.S. Saini, A. Sayed, I. Sharif, B. Srinivasan, M. Szwarc, G. Vadlamudi, V. Viajedor, R. Zeng
{"title":"A 125MHz burst mode 0.18/spl mu/m 128Mbit 2 bits per cell flash memory","authors":"H. Castro, K. Augustine, S. Balasubrahmanyam, T. Bressie, S. Chandramouli, G. Christensen, M. Dayley, D. Elmhurst, K. Fan, M. Goldman, C. Haid, R. Haque, M. Ishac, M. Khandaker, J. Kreifels, B. Li, K. Loe, T. Ly, F. Marvin, R. Melcher, S. Monasa, R. Nambiar, Q. Ngo, R. Padilla, B. Pathak, A. Rahman, R. Rajagopal, K. Ramamurthi, S.S. Saini, A. Sayed, I. Sharif, B. Srinivasan, M. Szwarc, G. Vadlamudi, V. Viajedor, R. Zeng","doi":"10.1109/VLSIC.2002.1015111","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015111","url":null,"abstract":"We describe the design of a high performance 2 bits per cell flash memory device capable of 8ns synchronous access rate capable of operation at up to 125MHz in burst mode and asynchronous page mode access rate of 14ns. The device is fabricated on Intel's 0.18/spl mu/m ETOX/spl trade/ VII Process technology.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127268627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A differential-capacitance read scheme for FeRAMs feram的差分电容读取方案
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015109
Y. Eslami, A. Sheikholeslami, S. Masui, T. Endo, S. Kawashima
{"title":"A differential-capacitance read scheme for FeRAMs","authors":"Y. Eslami, A. Sheikholeslami, S. Masui, T. Endo, S. Kawashima","doi":"10.1109/VLSIC.2002.1015109","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015109","url":null,"abstract":"A differential-capacitance read scheme keeps the plateline voltage constant at ground and begins sensing the stored data immediately after a wordline is raised, hence eliminating the time spent in conventional read schemes in raising the highly capacitive plateline and in charge sharing of the bitlines with the ferroelectric capacitors. The proposed read scheme is used in a 256/spl times/128-bit testchip that features both 2T-2C and 1T-1C cells in 0.35/spl mu/m technology. The read scheme achieves a 40% reduction in access time.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133181473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An integrated mixed-signal front-end for broadband modems 用于宽带调制解调器的集成混合信号前端
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015038
I. Mehr, D. Paterson, N. Abaskharoun, J. Lloyd, H. L'Bahy, A. DeSimone
{"title":"An integrated mixed-signal front-end for broadband modems","authors":"I. Mehr, D. Paterson, N. Abaskharoun, J. Lloyd, H. L'Bahy, A. DeSimone","doi":"10.1109/VLSIC.2002.1015038","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015038","url":null,"abstract":"An integrated mixed-signal transceiver for broadband communications is presented. The transceiver includes a configurable dual/single receive data path, a configurable dual/single transmit data path, and auxiliary functions including low-speed ADCs, low-speed DACs, serial port interface, clock and reference generation blocks. The receive data path provides constant input impedance and contains dual input buffers, dual programmable gain stages (PGAs), dual 12-bit ADC blocks, and a digital processing block, all sampling at up to 64 MHz. The transmit data path contains a digital processing block as well, and dual 14-bit DAC blocks with programmable gain, sampling at up to 128 MHz. The chip was implemented in double-poly triple-metal 0.35 /spl mu/m CMOS technology.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115368980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SOI circuit technology for batteryless mobile system with green energy sources 绿色能源无电池移动系统的SOI电路技术
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015105
N. Hama, A. Yajima, Y. Yoshida, F. Utsunomiya, J. Kodate, T. Tsukahara, T. Douseki
{"title":"SOI circuit technology for batteryless mobile system with green energy sources","authors":"N. Hama, A. Yajima, Y. Yoshida, F. Utsunomiya, J. Kodate, T. Tsukahara, T. Douseki","doi":"10.1109/VLSIC.2002.1015105","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015105","url":null,"abstract":"Energy-extracted circuit technology for green energy sources and ultralow-power SOI circuit technology with 1 mW level power dissipation provide self-powered operation of mobile equipment. A variable-stage switched-capacitor-type DC-DC converter scheme makes it possible to supply a constant voltage to LSIs for green energy sources. A 1-V 300 MHz-band voltage-controlled SAW oscillator circuit and a 0.5-V CPU fabricated with 0.35-/spl mu/m FD-SOI process are described. We verify the effectiveness of these circuits at self-powered wireless mobile system.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116552425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Bending-comb capacitor with a small parasitic inductance 具有小寄生电感的弯梳式电容器
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015033
Akira Imamura, M. Fujishima, K. Hoh
{"title":"Bending-comb capacitor with a small parasitic inductance","authors":"Akira Imamura, M. Fujishima, K. Hoh","doi":"10.1109/VLSIC.2002.1015033","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015033","url":null,"abstract":"A new metal-metal capacitor with a small parasitic inductance, named a bending-comb capacitor (BCC), is proposed based on a standard digital CMOS technology. The BCC is applicable to high frequency circuits due to its high self-resonance frequency. An analytical evaluation of the capacitance from the geometry size is also presented. The self-resonance frequency of the BCC of 0.85 pF with the size of 10 /spl mu/m /spl times/ 100 /spl mu/m is estimated as 374 GHz with a 0.13-/spl mu/m Cu-wiring CMOS process. This frequency is about six times higher than that estimated by the conventional comb capacitor.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123485131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 4.5 GHz 130 nm 32 KB L0 cache with a self reverse bias scheme 具有自反向偏置方案的4.5 GHz 130 nm 32 KB L0高速缓存
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI: 10.1109/VLSIC.2002.1015041
S. Hsu, A. Alvandpour, S. Mathew, Shih-Lien Lu, R. Krishnamurthy, S. Borkar
{"title":"A 4.5 GHz 130 nm 32 KB L0 cache with a self reverse bias scheme","authors":"S. Hsu, A. Alvandpour, S. Mathew, Shih-Lien Lu, R. Krishnamurthy, S. Borkar","doi":"10.1109/VLSIC.2002.1015041","DOIUrl":"https://doi.org/10.1109/VLSIC.2002.1015041","url":null,"abstract":"This paper describes a 32 KB dual-ported L0 cache for 4.5 GHz operation in 1.2 V, 130 nm CMOS. The local bitline uses a Self Reverse Bias scheme to achieve -220 mV access transistor underdrive without external bias voltage or gate-oxide overstress. 11% faster read delay and 104% higher DC robustness (including 7x measured active leakage reduction) is achieved over optimized high-performance dual-Vt scheme.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128798392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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