H. Castro, K. Augustine, S. Balasubrahmanyam, T. Bressie, S. Chandramouli, G. Christensen, M. Dayley, D. Elmhurst, K. Fan, M. Goldman, C. Haid, R. Haque, M. Ishac, M. Khandaker, J. Kreifels, B. Li, K. Loe, T. Ly, F. Marvin, R. Melcher, S. Monasa, R. Nambiar, Q. Ngo, R. Padilla, B. Pathak, A. Rahman, R. Rajagopal, K. Ramamurthi, S.S. Saini, A. Sayed, I. Sharif, B. Srinivasan, M. Szwarc, G. Vadlamudi, V. Viajedor, R. Zeng
{"title":"A 125MHz burst mode 0.18/spl mu/m 128Mbit 2 bits per cell flash memory","authors":"H. Castro, K. Augustine, S. Balasubrahmanyam, T. Bressie, S. Chandramouli, G. Christensen, M. Dayley, D. Elmhurst, K. Fan, M. Goldman, C. Haid, R. Haque, M. Ishac, M. Khandaker, J. Kreifels, B. Li, K. Loe, T. Ly, F. Marvin, R. Melcher, S. Monasa, R. Nambiar, Q. Ngo, R. Padilla, B. Pathak, A. Rahman, R. Rajagopal, K. Ramamurthi, S.S. Saini, A. Sayed, I. Sharif, B. Srinivasan, M. Szwarc, G. Vadlamudi, V. Viajedor, R. Zeng","doi":"10.1109/VLSIC.2002.1015111","DOIUrl":null,"url":null,"abstract":"We describe the design of a high performance 2 bits per cell flash memory device capable of 8ns synchronous access rate capable of operation at up to 125MHz in burst mode and asynchronous page mode access rate of 14ns. The device is fabricated on Intel's 0.18/spl mu/m ETOX/spl trade/ VII Process technology.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2002.1015111","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
We describe the design of a high performance 2 bits per cell flash memory device capable of 8ns synchronous access rate capable of operation at up to 125MHz in burst mode and asynchronous page mode access rate of 14ns. The device is fabricated on Intel's 0.18/spl mu/m ETOX/spl trade/ VII Process technology.