A 1.2 V 10-b 100-MSamples/s A/D converter in 0.12/spl mu/m CMOS

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015117

A. Blum, B. Engl, H. Eichfeld, R. Hagelauer, A. Abidi

引用次数: 6

Abstract

A CMOS analog-to-digital converter (ADC) utilizing folding, averaging and distributed interpolation is described. Fabricated in a digital 0.12 /spl mu/m CMOS process, the ADC occupies 0.32 mm/sup 2/ while dissipating 140 mW from a single 1.2 V supply. The experimental results show that the converter achieves 55dB SNR at sampling frequencies up to 100MHz.

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一个1.2 V 10-b 100-MSamples/s A/D转换器在0.12/spl mu/m CMOS

介绍了一种利用折叠、平均和分布插值的CMOS模数转换器(ADC)。采用数字0.12 /spl mu/m CMOS工艺制造，ADC占用0.32 mm/sup 2/，同时从单个1.2 V电源消耗140 mW。实验结果表明，该变换器在100MHz采样频率下信噪比可达55dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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