H. Mattausch, N. Omori, S. Fukae, T. Koide, T. Gyoten
{"title":"全平行模式匹配引擎与动态适应汉明或曼哈顿距离","authors":"H. Mattausch, N. Omori, S. Fukae, T. Koide, T. Gyoten","doi":"10.1109/VLSIC.2002.1015097","DOIUrl":null,"url":null,"abstract":"The proposed pattern-matching engine achieves distance-measure adaptability through pattern encoding and can therefore cover a wide range of high-performance real-time applications. Key to short nearest-match times is a compact fully-parallel associative-memory core. The performance of a 9.75 mm/sup 2/ test-circuit in 0.6 /spl mu/m CMOS technology is about equivalent to a 32 bit computer with ITOPS. The test-circuit suggests possible pattern length /spl ges/768 equivalent bit, >10/sup 7/ pattern/sec throughput, <1.13% winner-input-distance error and <1.35 mW power dissipation per reference pattern.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Fully-parallel pattern-matching engine with dynamic adaptability to Hamming or Manhattan distance\",\"authors\":\"H. Mattausch, N. Omori, S. Fukae, T. Koide, T. Gyoten\",\"doi\":\"10.1109/VLSIC.2002.1015097\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The proposed pattern-matching engine achieves distance-measure adaptability through pattern encoding and can therefore cover a wide range of high-performance real-time applications. Key to short nearest-match times is a compact fully-parallel associative-memory core. The performance of a 9.75 mm/sup 2/ test-circuit in 0.6 /spl mu/m CMOS technology is about equivalent to a 32 bit computer with ITOPS. The test-circuit suggests possible pattern length /spl ges/768 equivalent bit, >10/sup 7/ pattern/sec throughput, <1.13% winner-input-distance error and <1.35 mW power dissipation per reference pattern.\",\"PeriodicalId\":162493,\"journal\":{\"name\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2002.1015097\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2002.1015097","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fully-parallel pattern-matching engine with dynamic adaptability to Hamming or Manhattan distance
The proposed pattern-matching engine achieves distance-measure adaptability through pattern encoding and can therefore cover a wide range of high-performance real-time applications. Key to short nearest-match times is a compact fully-parallel associative-memory core. The performance of a 9.75 mm/sup 2/ test-circuit in 0.6 /spl mu/m CMOS technology is about equivalent to a 32 bit computer with ITOPS. The test-circuit suggests possible pattern length /spl ges/768 equivalent bit, >10/sup 7/ pattern/sec throughput, <1.13% winner-input-distance error and <1.35 mW power dissipation per reference pattern.