具有自反向偏置方案的4.5 GHz 130 nm 32 KB L0高速缓存

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015041

S. Hsu, A. Alvandpour, S. Mathew, Shih-Lien Lu, R. Krishnamurthy, S. Borkar

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引用次数: 2

摘要

本文描述了一个在1.2 V、130 nm CMOS上工作的32kb双端口L0缓存，工作频率为4.5 GHz。本地位线采用自反向偏置方案，实现-220 mV接入晶体管欠驱动，无外部偏置电压或栅极氧化物过应力。通过优化的高性能双vt方案，实现了11%更快的读取延迟和104%更高的直流稳健性(包括7倍的测量有源泄漏减少)。

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A 4.5 GHz 130 nm 32 KB L0 cache with a self reverse bias scheme

This paper describes a 32 KB dual-ported L0 cache for 4.5 GHz operation in 1.2 V, 130 nm CMOS. The local bitline uses a Self Reverse Bias scheme to achieve -220 mV access transistor underdrive without external bias voltage or gate-oxide overstress. 11% faster read delay and 104% higher DC robustness (including 7x measured active leakage reduction) is achieved over optimized high-performance dual-Vt scheme.

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来源期刊

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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