Four-way processor 800 MT/s front side bus with ground referenced voltage source I/O

Abstract

A 40 cm multi-drop bus shared by 5 test chips to emulate 4 processors and a chipset runs error free at 800 MT/s with 130 mV margin using Ground Referenced Voltage Source (GRVS) I/O scheme. For comparison, when the same test chip is programmed to use Gunning Transceiver Logic (GTL), the bus speed is 500 MT/s for the same 130 mV margin under identical conditions.