T. Honda, N. Sakimura, T. Sugibayashi, S. Miura, H. Numata, H. Hada, S. Tahara
{"title":"MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current","authors":"T. Honda, N. Sakimura, T. Sugibayashi, S. Miura, H. Numata, H. Hada, S. Tahara","doi":"10.1109/VLSIC.2002.1015072","DOIUrl":null,"url":null,"abstract":"MRAM-writing circuitry to compensate for the thermal variation of the magnetization-reversal current (MRC) is proposed. The writing current of the proposed circuitry is designed to decrease in proportion to an increase in temperature. This technique prevents multiple-write (MW) failures from degrading 1Gb MRAM yield where the standard deviation of MRC variation from other origins is less than 5%.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2002.1015072","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
MRAM-writing circuitry to compensate for the thermal variation of the magnetization-reversal current (MRC) is proposed. The writing current of the proposed circuitry is designed to decrease in proportion to an increase in temperature. This technique prevents multiple-write (MW) failures from degrading 1Gb MRAM yield where the standard deviation of MRC variation from other origins is less than 5%.