未来移动系统的超低功耗CMOS/SOI LSI设计

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015028

T. Douseki, J. Yamada, H. Kyuragi

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引用次数: 12

摘要

超低功耗CMOS/SOI电路技术采用完全耗尽的SOI和多阈值(MT) CMOS电路，可以将电源电压降低到0.5 V，将lsi的功耗降低到1 /spl sim/ 10 mW，而不会有任何速度损失。本文综述了超低功耗CMOS/SOI电路技术和一些基于MTCMOS/SOI电路的超低电压lsi。

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Ultralow-power CMOS/SOI LSI design for future mobile systems

Ultralow-power CMOS/SOI circuit technology that uses fully-depleted SOI and multi-threshold (MT) CMOS circuits makes it possible to lower the supply voltage to 0.5 V and reduce the power dissipation of LSIs to 1 /spl sim/ 10 mW without any speed loss. We overview the ultralow-power CMOS/SOI circuit technology and some ultralow-voltage LSIs based on MTCMOS/SOI circuits.

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来源期刊

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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