四路处理器800 MT/s前端总线与接地参考电压源I/O

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015048

T. Thomas, I. Young

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引用次数: 2

摘要

一个40厘米的多滴总线由5个测试芯片共享，以模拟4个处理器和一个芯片组，使用接地参考电压源(GRVS) I/O方案，以800 MT/s和130 mV余量运行无错误。相比之下，当相同的测试芯片被编程为使用Gunning Transceiver Logic (GTL)时，在相同的条件下，对于相同的130 mV裕量，总线速度为500 MT/s。

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Four-way processor 800 MT/s front side bus with ground referenced voltage source I/O

A 40 cm multi-drop bus shared by 5 test chips to emulate 4 processors and a chipset runs error free at 800 MT/s with 130 mV margin using Ground Referenced Voltage Source (GRVS) I/O scheme. For comparison, when the same test chip is programmed to use Gunning Transceiver Logic (GTL), the bus speed is 500 MT/s for the same 130 mV margin under identical conditions.

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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