Programmable termination for CML I/O's in high speed CMOS transceivers

Abstract

This paper describes I/O circuits that can be used in high-speed transceivers to communicate with next generation and legacy devices. We describe the transmitter and receiver front-end circuits that are designed to operate with dual termination voltage supplies. The receiver characterization, ESD protection and system level power up issues related to gate-oxide and electro-migration reliability are discussed.