S. Wuensche, M. Jacunski, H. Streif, A. Sturm, J. Morrish, M. Roberge, M. Clark, T. Nostrand, E. Stahl, S. Lewis, J. Heath, M. Wood, T. Vogelsang, E. Thoma, J. Gabric, M. Kleiner, M. Killian, P. Poechmueller, W. Mueller, G. Bronner
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A 110 nm 512 Mb DDR DRAM with vertical transistor trench cell
This paper describes a 512 Mb DDR SDRAM in 110 nm technology based on a highly cost efficient 8F/sup 2/ trench capacitor cell with a double gate vertical pass transistor. The product also features a bitline voltage generator using a distributed output transistor with a power supply IR-drop correction scheme. A read/write selective column activation circuit is employed to optimize high frequency operation.
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