一个浮动门修整，14位，250毫秒/秒的数模转换器在标准的0.25 /spl μ m CMOS

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015118

J. Hyde, T. Humes, C. Diorio, M. Thomas, M. Figueroa

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引用次数: 13

摘要

我们描述了一种采用0.25 /spl mu/m CMOS逻辑工艺制造的浮栅修整，14位，250 Ms/s电流导向DAC。我们使用存储在浮栅pfet上的模拟电荷将静态INL修剪为/spl plusmn/0.3 LSB。该DAC占芯片面积的0.44 mm/sup / 2，在250 MHz时消耗53 mW，允许片上电气微调，并在250 Ms/s时实现72 dB SFDR。

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A floating-gate trimmed, 14-bit, 250 Ms/s digital-to-analog converter in standard 0.25 /spl mu/m CMOS

We describe a floating-gate trimmed, 14-bit, 250 Ms/s current-steered DAC fabricated in a 0.25 /spl mu/m CMOS logic process. We trim the static INL to /spl plusmn/0.3 LSB using analog charge stored on floating-gate pFETs. The DAC occupies 0.44 mm/sup 2/ of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves 72 dB SFDR at 250 Ms/s.

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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