双电源电压时钟的5 GHz 130纳米整数执行核心

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015121

Ram K. Krishnamurthy, S. Hsu, M. Anders, B. Bloechel, B. Chatterjee, M. Sachdev, S. Borkar

{"title":"双电源电压时钟的5 GHz 130纳米整数执行核心","authors":"Ram K. Krishnamurthy, S. Hsu, M. Anders, B. Bloechel, B. Chatterjee, M. Sachdev, S. Borkar","doi":"10.1109/VLSIC.2002.1015121","DOIUrl":null,"url":null,"abstract":"This paper describes dual-V/sub cc/ clocking on a 1.2 V, 5 GHz integer execution core fabricated in 130 nm CMOS to achieve up to 71% measured clock power (including 15% active leakage) reduction. A write-port style pass-transistor latch and split-output level-converting local clock buffer are described for robust, DC power free low-V/sub cc/ clock operation.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"40","resultStr":"{\"title\":\"Dual supply voltage clocking for 5 GHz 130 nm integer execution core\",\"authors\":\"Ram K. Krishnamurthy, S. Hsu, M. Anders, B. Bloechel, B. Chatterjee, M. Sachdev, S. Borkar\",\"doi\":\"10.1109/VLSIC.2002.1015121\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes dual-V/sub cc/ clocking on a 1.2 V, 5 GHz integer execution core fabricated in 130 nm CMOS to achieve up to 71% measured clock power (including 15% active leakage) reduction. A write-port style pass-transistor latch and split-output level-converting local clock buffer are described for robust, DC power free low-V/sub cc/ clock operation.\",\"PeriodicalId\":162493,\"journal\":{\"name\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"40\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2002.1015121\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2002.1015121","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 40

摘要

本文描述了在130 nm CMOS中制造的1.2 V, 5 GHz整数执行核心上的双V/sub / cc/时钟，可实现高达71%的测量时钟功率(包括15%的有源泄漏)降低。一个写端口风格的通管锁存器和分路输出电平转换的本地时钟缓冲器被描述为鲁棒，直流无电源低v /sub /时钟操作。

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Dual supply voltage clocking for 5 GHz 130 nm integer execution core

This paper describes dual-V/sub cc/ clocking on a 1.2 V, 5 GHz integer execution core fabricated in 130 nm CMOS to achieve up to 71% measured clock power (including 15% active leakage) reduction. A write-port style pass-transistor latch and split-output level-converting local clock buffer are described for robust, DC power free low-V/sub cc/ clock operation.

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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