采用矩形扩散单元和增量阵列电压方案的0.4 v逻辑库友好SRAM阵列

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015076

M. Yamaoka, K. Osada, K. Ishibashi

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引用次数: 17

摘要

我们设计了一个逻辑库友好的SRAM阵列。阵列采用矩形扩散单元(RD-cell)和增量阵列升压方案(DBA-scheme)。在rd细胞中，细胞比例为1.0，它减少了细胞比例的不平衡。较低的电源电压会使静态噪声裕度下降，而dba方案可以对其进行补偿。采用RD-cell和dba方案相结合的32kb测试芯片，在4.5 mhz频率下实现0.4 v工作，功耗140-/spl mu/W，待机电流0.9-/spl mu/ a。

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0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array-voltage scheme

We designed a logic library friendly SRAM array. The array uses rectangular-diffusion cell (RD-cell) and delta-boosted-array-voltage scheme (DBA-scheme). In the RD-cell, the cell ratio is 1.0, and it reduces the imbalance of the cell ratio. A low supply voltage deteriorates the static noise margin, however, the DBA-scheme compensates it. Using the combination of RD-cell and DBA-scheme, a 32-kB test chip achieves 0.4-V operation at 4.5-MHz frequency and 140-/spl mu/W power dissipation and 0.9-/spl mu/A standby current.

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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