{"title":"设计一个3ghz, 130nm, Intel/sup /spl reg// Pentium/sup /spl reg// 4处理器","authors":"D. Deleganes, J. Douglas, B. Kommandur, M. Patyra","doi":"10.1109/VLSIC.2002.1015065","DOIUrl":null,"url":null,"abstract":"The design of an IA32 processor fabricated in a state-of-the art 130 nm CMOS process with improved six layers of dual-damascene copper metallization is described. This paper describes the methodology employed to simultaneously achieve high frequency and low power in the Pentium/sup /spl reg// 4 processor, suitable for all segments-server, desktop, and mobile-meeting diverse challenges of performance, power delivery, and dissipation.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Designing a 3 GHz, 130 nm, Intel/sup /spl reg// Pentium/sup /spl reg// 4 processor\",\"authors\":\"D. Deleganes, J. Douglas, B. Kommandur, M. Patyra\",\"doi\":\"10.1109/VLSIC.2002.1015065\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of an IA32 processor fabricated in a state-of-the art 130 nm CMOS process with improved six layers of dual-damascene copper metallization is described. This paper describes the methodology employed to simultaneously achieve high frequency and low power in the Pentium/sup /spl reg// 4 processor, suitable for all segments-server, desktop, and mobile-meeting diverse challenges of performance, power delivery, and dissipation.\",\"PeriodicalId\":162493,\"journal\":{\"name\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"volume\":\"98 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2002.1015065\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2002.1015065","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The design of an IA32 processor fabricated in a state-of-the art 130 nm CMOS process with improved six layers of dual-damascene copper metallization is described. This paper describes the methodology employed to simultaneously achieve high frequency and low power in the Pentium/sup /spl reg// 4 processor, suitable for all segments-server, desktop, and mobile-meeting diverse challenges of performance, power delivery, and dissipation.