采用片上调节双环锁相环的0.4- 4gb /s CMOS四路收发器单元

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015054

Ken-Hao Chang, Jason Wei, Charlie Huang, S. Li, K. Donnelly, M. Horowitz, Yingxuan Li, S. Sidiropoulos

{"title":"采用片上调节双环锁相环的0.4- 4gb /s CMOS四路收发器单元","authors":"Ken-Hao Chang, Jason Wei, Charlie Huang, S. Li, K. Donnelly, M. Horowitz, Yingxuan Li, S. Sidiropoulos","doi":"10.1109/VLSIC.2002.1015054","DOIUrl":null,"url":null,"abstract":"A quad high-speed transceiver cell is designed and implemented in 0.13 /spl mu/m CMOS technology. To achieve low jitter while maintaining low power consumption, dual on-chip regulators are used for each dual-loop PLL. The prototype chip demonstrates that the links can operate from 400 Mb/s to 4 Gb/s with a bit error rate <10/sup -14/. The quad cell consumes 390 mW at 2.5 Gb/s (95 mW/link) under typical operating conditions with a 400 mV output swing driving double terminated links.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"93","resultStr":"{\"title\":\"A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs\",\"authors\":\"Ken-Hao Chang, Jason Wei, Charlie Huang, S. Li, K. Donnelly, M. Horowitz, Yingxuan Li, S. Sidiropoulos\",\"doi\":\"10.1109/VLSIC.2002.1015054\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A quad high-speed transceiver cell is designed and implemented in 0.13 /spl mu/m CMOS technology. To achieve low jitter while maintaining low power consumption, dual on-chip regulators are used for each dual-loop PLL. The prototype chip demonstrates that the links can operate from 400 Mb/s to 4 Gb/s with a bit error rate <10/sup -14/. The quad cell consumes 390 mW at 2.5 Gb/s (95 mW/link) under typical operating conditions with a 400 mV output swing driving double terminated links.\",\"PeriodicalId\":162493,\"journal\":{\"name\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"93\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2002.1015054\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2002.1015054","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 93

摘要

以0.13 /spl mu/m CMOS工艺设计并实现了四高速收发模块。为了在保持低功耗的同时实现低抖动，每个双环锁相环采用双片上稳压器。原型芯片表明，链路可以在400mb /s到4gb /s之间运行，误码率<10/sup -14/。在典型工作条件下，四单元电池以2.5 Gb/s (95 mW/链路)的速度消耗390 mW，输出摆幅为400 mV，驱动双端链路。

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A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

A quad high-speed transceiver cell is designed and implemented in 0.13 /spl mu/m CMOS technology. To achieve low jitter while maintaining low power consumption, dual on-chip regulators are used for each dual-loop PLL. The prototype chip demonstrates that the links can operate from 400 Mb/s to 4 Gb/s with a bit error rate <10/sup -14/. The quad cell consumes 390 mW at 2.5 Gb/s (95 mW/link) under typical operating conditions with a 400 mV output swing driving double terminated links.

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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